Patents Assigned to Freescale
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Patent number: 9469523Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.Type: GrantFiled: April 23, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Lianjun Liu
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Patent number: 9471812Abstract: An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.Type: GrantFiled: March 6, 2012Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Chen He
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Patent number: 9474016Abstract: The present application relates to an orthogonal frequency division multiplexing (OFDM) receiver and a method of operating the receiver for performing a cell search. A coarse correlator block is provided to detect one cell out of a by plurality of wireless communication cells by determining first correlation metric values by applying a partial correlation comprising part-wise correlating sample data with each one of a first set of phase-rotated reference sequences and non-coherent combining. The maximum of the first correlation values yields to a cell identifier value. A fine correlator block is provided to estimate a fine time offset value for the one wireless communication cell by determining second correlation values by applying a correlation comprising correlating the he sample data with each one of a second set of phase-rotated reference sequences. The maximum of the second correlation values value yields to a fine time offset.Type: GrantFiled: April 14, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ciprian Iancu Mindru, Tudor Bogatu, Lucian Panduru, Balasubramanian Vaidhyanathan
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Patent number: 9474031Abstract: A method for performing foreign object detection in an inductive wireless power transfer system is disclosed. In the embodiment, the method involves obtaining measurements from a base station of a wireless power transfer system during charging and determining transmitter energy loss in a power transmitter, Ptxloss, using the obtained measurements, wherein the transmitter energy loss, Ptxloss, is a function of at least Vcap and PTx, wherein Vcap is proportional to the voltage amplitude across the capacitor of an LC tank circuit in a power transmitter and PTx is the total power supplied to the power transmitter. The method also involves detecting the presence of a foreign object in response to the estimated transmitter energy loss.Type: GrantFiled: April 16, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Aliaksei Vladimirovich Sedzin, Klaas Brink, Rene Geraets, Patrick Niessen, Oswald Moonen
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Patent number: 9473466Abstract: A decentralized method for IPSec processing in virtual environments includes assigning a unique identifier to each of a set of compute nodes. Each compute node can emulate one or more virtual machines that generate IP packets for forwarding over a network (e.g., the Internet). An IP packet, received from a trusted source at a compute node, is encrypted and a trailer is appended to the encrypted packet. The trailer includes the unique identifier of the compute node. The encrypted packet with appended trailer is forwarded to a secure gateway that can perform an anti-replay check using stored parameters corresponding to the unique identifier in the trailer. In inbound processing, the unique identifier is inserted into a trailer appended to an encrypted packet by the security gateway and a VPN server directs the incoming encrypted packet to the appropriate compute node for forwarding to the virtual machine.Type: GrantFiled: October 10, 2014Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Jyothi Vemulapalli, Srinivasa Rao Addepalli
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Patent number: 9473396Abstract: A system for steering data packets in a communication network that includes compute nodes having processors for executing application and service virtual machines (VMs), and traffic steering accelerators. A virtual local area network-identifier (VLAN-ID) assignment module generates records and associates the records with the service VMs. Each record includes an input VLAN-ID, an output VLAN-ID, and a port number corresponding to one of the service VMs. A service-chaining module generates chaining rules associated with n-Tuples. A traffic steering controller generates a chain of the records based on the service chaining rules. The traffic steering accelerator then steers the data packets based on the input and output VLAN-IDs included in the data packet.Type: GrantFiled: May 6, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Satya Srinivasa Murthy Nittala, Srinivasa R. Addepalli, Balaji Padnala
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Patent number: 9473164Abstract: A data processing system having an analog-to-digital converter (ADC) and method for testing the ADC are provided. The data processing system also comprises a digital-to-analog converter (DAC) and test logic. The DAC has a first voltage range, an input for receiving a test code, and an output. The ADC has a second voltage range larger than the first voltage range, an input coupled to the output of the DAC, and an output for providing a series of output codes over the second voltage range. The test logic is coupled to the ADC and is for controlling testing of the ADC using the DAC. A plurality of series of test codes are provided to the DAC for testing portions of the second voltage range output from the ADC. A beginning series of test codes is for testing a beginning portion of the second voltage range and subsequent series of test codes are for testing subsequent portions of the second voltage range.Type: GrantFiled: June 26, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Tao Chen, Xiankun Jin
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Patent number: 9472662Abstract: A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.Type: GrantFiled: September 30, 2015Date of Patent: October 18, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Evgueniy Stefanov, Edouard Denis De Fresart, Moaniss Zitouni
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Patent number: 9472528Abstract: An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board.Type: GrantFiled: June 5, 2014Date of Patent: October 18, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Weng F. Yap
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Patent number: 9473121Abstract: A scannable flip-flop circuit and method for low power scan operation are provided. The scannable flip-flop includes a flip-flop for receiving an input signal, and for generating a flip-flop output signal. The scannable flip-flop also includes a voltage selection circuit coupled to the flip-flop. The voltage selection circuit supplies a first voltage to the flip-flop during a first state of a voltage selection signal, and supplies a second voltage to the flip-flop during a second state of the voltage selection signal. A series of scannable flip-flops may be arranged in a scan chain for testing during a scan test mode.Type: GrantFiled: July 15, 2015Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kumar Abhishek, Gaurav Goyal, Syed Shakir Iqbal
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Publication number: 20160299859Abstract: There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module (13) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module (14) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.Type: ApplicationFiled: November 22, 2013Publication date: October 13, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Daniel Dumitru Popa, ALEXANDRA DRACEA, DRAGOS MILOIU
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Publication number: 20160299828Abstract: An apparatus for debugging operational code of a target program comprises a memory storing the operational code and a set of instructions representing a debugger program for debugging the operational code. A microprocessor is configured to execute the operational code and the debugger program. The debugger program can inject a jump to a breakpoint handling routine into the operational code and let a compiler program create code pieces for the breakpoint handling routine.Type: ApplicationFiled: November 29, 2013Publication date: October 13, 2016Applicant: Freescale Semiconductor, Inc.Inventors: MIHAIL-MARIAN NISTOR, DRAGOS MILOIU
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Patent number: 9463976Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.Type: GrantFiled: June 27, 2014Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Robert F. Steimle, Paul M. Winebarger
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Patent number: 9465500Abstract: Embodiments of a touchscreen control device and associated method of operation enable two-touch gesture detection on a four-wires resistive touchscreen. Illustrative devices and methods enable detection when a resistive touchscreen is touched in two separate points. Embodiments of an electronic circuit can comprise a controller configured for coupling to a four-wires resistive touchscreen and at least two resistors. The controller can be further configured to detect multiple touches on the four-wires resistive touchscreen and measure zoom gestures comprising measuring distances between two-touches and obtaining angle of rotation and total distance between the two-touches.Type: GrantFiled: April 21, 2012Date of Patent: October 11, 2016Assignee: Freescale Semicondcutor, Inc.Inventors: Eduardo Muriel Hernandez, Juan Cazares Blanco, Antonio Castro Trejo
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Patent number: 9466569Abstract: A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate. The via is filled with conductive material and extends to at least the first major surface of the substrate. A thermal expansion inhibitor is over and in direct contact with the via proximate the first major surface. The thermal expansion inhibitor exerts a compressive stress on the conductive material closest to the thermal expansion inhibitor compared to the conductive material at a further distance from the thermal expansion inhibitor.Type: GrantFiled: November 12, 2014Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Mehul D. Shroff, Douglas M. Reber
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Patent number: 9467252Abstract: A plurality of turbo decoder engines store extrinsic values when concurrently decoding a received signal encoded within rows and columns of an interleaving matrix where interleaved values stay in a same re-ordered row during interleaving. An extrinsic reader and extrinsic writer accesses extrinsic memories using extrinsic addresses. A deinterleaver accesses the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix that was used to encode the received signal, each of the rows corresponding to one of the plurality of turbo decoder engines, and, in embodiments, can group the extrinsic values such that all the extrinsic values in each one of the rows of the interleaving matrix go in a same one of the plurality of the extrinsic addressable memory. The deinterleaver can skip read of extrinsic values corresponding to dummy entries in the interleaving matrix.Type: GrantFiled: November 26, 2014Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Robert Bahary, Eric J Jackowski
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Patent number: 9466588Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.Type: GrantFiled: February 23, 2015Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Fernando A. Santos, Audel A. Sanchez, Lakshminarayan Viswanathan
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Patent number: 9466413Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.Type: GrantFiled: June 28, 2013Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Fred T. Brauchler, John M. Pigott, Darrel R. Frear, Vivek Gupta, Randall C. Gray, Norman L. Owens, Carl E. D'Acosta
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Patent number: 9463973Abstract: A mechanism for reducing stiction in a MEMS device by decreasing an amount of carbon from TEOS-based silicon oxide films that can accumulate on polysilicon surfaces during fabrication is provided. A carbon barrier material film is deposited between one or more polysilicon layer in a MEMS device and the TEOS-based silicon oxide layer. This barrier material blocks diffusion of carbon into the polysilicon, thereby reducing accumulation of carbon on the polysilicon surfaces. By reducing the accumulation of carbon, the opportunity for stiction due to the presence of the carbon is similarly reduced.Type: GrantFiled: October 31, 2014Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Ruben B. Montez, Robert F. Steimle
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Patent number: 9466687Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.Type: GrantFiled: January 16, 2014Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo