Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract: A video processing system dynamically adjusts video processing prediction error reduction computations in accordance with the amount of motion represented in a set of image data and/or available memory resources to store compressed video data. In at least one embodiment, video processing system adjusts utilization of prediction error computational resources based on the size of a prediction error between a first set of image data, such as current set of image data being processed, and a reference set of image data relative to an amount of motion in a current set of image data. Additionally, in at least one embodiment, the video processing adjusts utilization of prediction error computation resources based upon a fullness level of a data buffer relative to the amount of motion in the current set of image data.

Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, control circuit, signal evaluation circuitry, a digital to analog converter, signal filters, an amplifier, demodulation circuitry and memory. The system is configured to generate high and low-frequency signals, combine them, and provide the combined input signal to a MEMS sensor. The MEMS sensor is configured to provide a modulated output signal that is a function of the combined signal. The system is configured to demodulate and filter the modulated output signal, compare the demodulated, filtered signal with the input signal to determine amplitude and phase differences, and determine, based on the amplitude and phase differences, various parameters of the MEMS sensor. A method for determining MEMS sensor parameters is also provided.

Abstract: An angular rate sensor includes a substrate, a drive mass flexibly coupled to the substrate, and a sense mass suspended above the substrate and flexibly coupled to the drive mass via flexible support elements. An electrode structure is mechanically coupled to, but electrically isolated from, the drive mass and is spaced apart from the substrate so that it is not in contact with the substrate. The electrode structure is configured to produce a signal that indicates movement of the sense mass relative to the electrode when the sensor is subjected to angular velocity. When the angular rate sensor experiences quadrature error, the drive mass, the sense mass, and the electrode structure move together relative to the sense axis. Since the sense mass and the electrode structure move together in response to quadrature error, there is little relative motion between the sense mass and the electrode structure so that quadrature error is largely eliminated.

Abstract: There is provided a network node of a wireless communication network, such as a UMTS network. The network node is arranged to perform a method of detecting Signal Discontinuous Transmission on a channel in the wireless communication network. The method comprises the receiving of a signal on the channel and the processing of a current slot of the signal, the current slot comprising a number of pilot bits and non-pilot bits. A bit error rate, a signal to noise ratio and an amplitude modulus is calculated using the pilot bits and non-pilot bits. A decision is made about whether the signal indicates a discontinuous transmission on the channel using the signal to noise ratio, the bit error rate and the amplitude modulus.

Abstract: An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Abstract: A current-to-voltage converter receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage to be used as a control signal to a varactor in a voltage controlled oscillator, VCO, to compensate for temperature-induced frequency drift in the VCO. A feedback arrangement with hysteresis is provided for controlling the selection of the temperature coefficient factor and operates by comparing the temperature-dependent voltage with a reference voltage. The reference voltage may be pre-set and equivalent to a known operating temperature. A switching signal is generated when Vout approaches the reference voltage and in response a control module generates a selection signal for selecting a different temperature coefficient factor.

Abstract: The present invention pertains to a linear power regulator device, comprising an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output, wherein the linear power regulator device comprises an external connection connectable or connected to an external pass device; and wherein the driver device is arranged to drive an external pass device via the driver output and the external connection. The invention also pertains to a corresponding electronic device.

Abstract: A power management controller (PMC) for resetting various voltage domains of an integrated circuit (IC) generates and transmits first and second voltage domain input signals to first and second voltage domains, respectively, and generates corresponding reset signals for resetting the first and second voltage domains. The PMC generates a first master reset signal indicative of resetting the first and second voltage domains when the first and second voltage domains are booting. The PMC generates a second master reset signal indicative of resetting the first and second voltage domains when the IC is in a functional mode. The PMC determines whether the first and second voltage domains are non-functional and if at least one is non-functional, then the PMC masks a respective one of the first and second reset signals.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.

Abstract: A sensing device includes a sensor die having a sensing region formed at a first surface of the sensor die. The sensing device further includes an encapsulant covering the sensing die, the encapsulant having a cavity formed therein, wherein the cavity exposes the sensing region. A sensitive membrane material is deposited within the cavity over the sensing region. A method of manufacturing sensing devices entails mounting a plurality of sensing dies to a carrier, encapsulating the dies in an encapsulant, forming cavities in the encapsulant, the cavities exposing a sensing region of each sensor die, and depositing the sensitive membrane material within each of the cavities. The encapsulating and forming operations can be performed simultaneously using a film-assisted molding (FAM) process, and the depositing operation is performed following FAM at an ambient temperature that is lower than the temperature needed to perform FAM.

Abstract: A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Abstract: A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Abstract: There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.

Abstract: An integrated circuit includes an input/output “I/O” cell arranged to drive an output signal and an activity analysis unit arranged to generate an activity factor based on the output signal. The activity factor represents a switching activity intensity of the I/O cell. The switching activity intensity is associated with an ageing effect of the I/O cell. The circuit further includes a calibration unit arranged to generate a switching pattern signal based on the generated activity factor and an I/O calibration cell arranged to be driven by the switching pattern signal, wherein the switching pattern signal emulates the ageing effect of the I/O cell.