Patents Assigned to Fujitsu
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Patent number: 6459639Abstract: Sense amplifiers provided in a same bank are divided into groups, the sense amplifiers in each group are connected to a common power supply wiring for the sense amplifier which is independent by the group, and the power supply wiring for the sense amplifier of each group is connected to a power supply circuit which is independent so that the ratio of the activated sense amplifiers to the driven power supply circuits is equalized in a reading-out/writing-in operation in which at least one sub-block in the bank is activated and a refreshing operation in which the sub-blocks are concurrently activated, which makes it possible to prevent an insufficiency/excess of a driving capacity of overdrive, without providing a special controlling circuit separately.Type: GrantFiled: January 31, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Koichi Nishimura
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Patent number: 6457633Abstract: A method of forming a semiconductor device mounts solder balls on a resin board which has holes formed therethrough and conductive sheets formed therebeneath to cover bottom ends of the holes. The method includes the steps of applying solder paste on the holes, melting the solder paste by heat to make solder of the solder paste flow into the holes and establish contact with the conductive sheets, and connecting the solder balls to the solder filled in the holes.Type: GrantFiled: March 24, 1999Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Akira Takashima, Kazuya Kamimura, Yoshikazu Kumagaya
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Patent number: 6459161Abstract: The semiconductor device of the present invention with an IC chip provided on one side of a substrate, comprises a plurality of connection terminals, which are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than corners of the array.Type: GrantFiled: November 9, 1999Date of Patent: October 1, 2002Assignees: NEC Corporation, Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Masayoshi Hirata, Yasuhiro Suzuki, Tetsuya Hiraoka, Mitsutaka Sato
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Patent number: 6459319Abstract: The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.Type: GrantFiled: April 30, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Atsumasa Sako
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Patent number: 6459582Abstract: A clamping system decouples the clamping forces in an electrical circuit assembly coupled to a heatsink. A heatsink clamping assembly applies controllable and predictable force on the electrical circuit assembly including an integrated circuit device (“chip”). The applied force is controlled to effectively ensure intimate contact between the chip and the heatsink to facilitate efficient chip cooling. The force applied to the chip is decoupled from the much higher force required to clamp the electrical interposer interconnect structure between the electrical circuit assembly and the printed circuit board.Type: GrantFiled: July 19, 2000Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Hassan O. Ali, Richard L. Bechtel
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Patent number: 6459329Abstract: An internal power supply auxiliary circuit supplies a current to a power generator circuit. A pulse signal generator receives an input signal and outputs a first control signal. A driver circuit connected to the pulse signal generator receives the first control signal, an external supply voltage and a source voltage, and generates a drive pulse signal. A current supply driver circuit receives the drive pulse signal and the external supply voltage and outputs the supply current to the power generator circuit. A gate voltage regulator circuit connected to the driver circuit receives a reference voltage and produces the source voltage. The gate voltage regulator causes the source voltage to substantially match the reference voltage so that the current supplied to the power generator circuit does not exceed a predetermined value.Type: GrantFiled: March 10, 1998Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Isamu Kobayashi, Syuichi Saito, Hajime Sato
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Patent number: 6460137Abstract: A random-number generator generates first and second title keys on the basis of random numbers. A first DES encryption circuit for the title encrypts input data with the first title key. Initial values of this item of input data are a data identifier (ID) and program clock reference (PCR) that are extracted from a packet header. After completing the encryption of the initial values, a result of an encryption by a second DES encryption circuit for title serves as the input data for the first DES encryption circuit for title. The second DES encryption circuit for title encrypts a value of result of the encryption by the first DES encryption circuit for title with the second title key. An exclusive OR circuit outputs an exclusive OR of the data stored in the packet and a value of result of the encryption by the second DES encryption circuit for title. This exclusive OR turns out encrypted data.Type: GrantFiled: March 19, 1996Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Ryota Akiyama, Akio Munakata, Yuzuru Koga, Masayuki Ishizaki, Makoto Yoshioka
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Patent number: 6458019Abstract: A surface of a work piece, in which a plurality of magnetic head elements are formed on a substrate, is linearly ground. The surface is linearly ground by an outer circumferential face of a disk-shaped rotary grind stone. By the linear grind, linear grind traces are formed in the work piece. By selecting the direction of the grind traces, amount and direction of warping the work piece can be controlled. By making the direction of the grind traces parallel to a direction of cutting of the work piece to form a plurality of blocks, in each of which a plurality of magnetic head elements are arranged, stress in the blocks are released and the amount of warping of the blocks can be reduced.Type: GrantFiled: March 19, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Kazuhisa Gonda
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Patent number: 6459120Abstract: A regular tetrahedral groove is formed in a wafer, and a memory unit is formed, which includes a channel layer as a first semiconductor layer to serve as a channel, a three-layer structure floating layer as a second semiconductor layer to serve as a floating gate, and an electrode contact layer as a third semiconductor layer to secure drain contact. The floating layer is formed into a three-layer structure of a p-AlGaAs layer, an i-InGaAs layer and a p-AlGaAs layer. It is possible to provide a semiconductor device capable of securing its sufficient functionality at a room temperature by using a quantum dot structure, and achieving an ultimate high-density integration with high reliability. Also provided is a method capable of easily manufacturing semiconductor devices having such a construction.Type: GrantFiled: August 10, 2000Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Masashi Shima
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Patent number: 6459112Abstract: A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.Type: GrantFiled: January 20, 2000Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Osamu Tsuboi, Tomohiko Tsutsumi, Kazutaka Yoshizawa
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Patent number: 6457852Abstract: A chemical supplying apparatus includes first and second mixing tanks for mixing and supplying chemical slurries used in a semiconductor fabrication process. The slurries are alternately provided from the first and second mixing tanks such that the slurry is continuously available to a processing apparatus for maximum efficiency. While one of the tanks is supplying the slurry, the other tank is cleaned and then used to prepare a new batch of the slurry.Type: GrantFiled: March 31, 1998Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Naoki Hiraoka, Takeshi Hiraide
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Patent number: 6459107Abstract: A photodetector includes a substrate and an optical absorption layer provided on the substrate, wherein the optical absorption layer is formed of a mixed crystal of Si, Ge and C.Type: GrantFiled: February 27, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Yoshihiro Sugiyama, Yoshiki Sakuma
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Patent number: 6457233Abstract: A solder bonding method comprises the step of solder bonding a first electrode 30 to a second electrode 16 having a solder bump 18 of mainly Sn formed on the upper surface thereof. The first electrode 30 and/or the second electrode 16 includes metal layers 14, 26 formed of an alloy layer containing Ni and P, an alloy layer containing Ni and B, or an alloy layer containing N, W and P. The metal layer of the alloy layer containing impurities, such as P, etc. can prevent the Ni of the metal layer from combining with the Sn in the solder bump. Accordingly, good bonded states can be obtained.Type: GrantFiled: December 3, 1999Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Kozo Shimizu
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Patent number: 6459220Abstract: This invention relates to a control method, control device, and drive circuit for controlling the rpm of a spindle motor in order to reduce the rise time of the spindle motor. There is a discharge circuit (91-2) in the charge pump (91) of a spindle-motor driver (38). A control circuit (12) detects when the rpm of the spindle motor reaches near a target rpm, and discharges the charge pump (91). In this way, the rotation error near the target rpm is discharged, so it is possible to control and suppress overshoot. This makes it possible to reduce the rise time.Type: GrantFiled: April 11, 2000Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Hideshi Mochizuki, Hiroshi Kumita, Shigenori Yanagi, Tomoki Yokoyama
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Patent number: 6459608Abstract: Data stored in a ferroelectric capacitor having its one electrode connected to a plate line and its other electrode connected to a bit line is read out by inputting a pulse to the plate line and then performing a sense operation to amplify the data. The sense operation is performed after a signal from the non-switching ferroelectric capacitor is decreased from its peak value right after pulsing the plate line. A predetermined time is ensured from input of the pulse to the sense operation. With this arrangement, the signal output can be decreased. The signal output margin can be ensured, and the service life of a device can be increased by decreasing the output from the bit line due to the imprint effect on the capacitor.Type: GrantFiled: March 28, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Tetsuro Tamura
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Patent number: 6459641Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.Type: GrantFiled: April 16, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Waichirou Fujieda, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Takayuki Nagasawa
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Patent number: 6458237Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.Type: GrantFiled: March 20, 1998Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
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Patent number: 6459736Abstract: A moving picture decoding apparatus includes an input part which adds at least one picture tag to a bit stream, having a plurality of pictures, which has been subjected to intraframe or interframe encoding, the picture tag or tags having a value monotonously changing on a picture-by-picture basis, independent of picture content, a buffer memory storing the bit stream and a controller controlling one or more of the plurality of pictures stored in the buffer memory by referring to the corresponding picture tag or tags.Type: GrantFiled: June 9, 1998Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Mitsuhiko Ohta, Tadayoshi Kono, Masanori Ishizuka, Hirohiko Inagaki, Koichi Yamashita
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Patent number: 6459466Abstract: The present invention provides a liquid-crystal display device having a first insulation base, a second insulation base facing the first insulation base such that a space is defined between the first insulation base and the second insulation base, in the following conditions: The space between the first insulation base and the second insulation base is filled with a liquid-crystal layer and is sealed with the first insulation base, the second insulation base and supporting members. Accordingly, a display area is provided on the sealed surface area of the first insulation base so as to face the second insulation base and includes thin-film transistors. Also, a terminal area is provided on the not-sealed surface area of the first insulation base and has terminal electrodes that connect electrically to corresponding thin-film transistors formed in the display area, respectively.Type: GrantFiled: July 6, 1999Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Tetsuya Fujikawa
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Patent number: 6460129Abstract: A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit.Type: GrantFiled: October 21, 1997Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Shinichi Moriwaki, Masahiro Yanagida, Shuntaro Fujioka, Hidenobu Ohta