Abstract: A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

Abstract: The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.

Abstract: A synchronous semiconductor memory device for switching an output route of read data based on latency information includes a read amplifier, a register block, a first signal route, a second signal route, and a switching circuit. The read amplifier amplifies the data read from a memory cell. The register block latches the amplified data and outputs the latched data at a timing corresponding to latency information. The first signal route is connected to the read amplifier to bypass the register block. The second signal route is connected to the read amplifier via the register block. The switching circuit is connected to the first and second signal routes and outputs either the amplified data or the latched data.

Abstract: A semiconductor device for reliably detecting an erroneous entry into a test mode in ordinary usage and for performing various operational tests at the time of shipment includes an internal circuit and a test-mode control circuit. The test-mode control circuit includes a first control circuit and a second control circuit. The test-mode control circuit operates the internal circuit in the test mode in accordance with a test mode command. The first control circuit inactivates at least a part of the internal circuit in accordance with the test mode command. The second control circuit activates at least the part of the internal circuit in accordance with a release command supplied following the test mode command.

Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.

Abstract: A discharge control circuit that securely prevents an over discharge of a battery. The control circuit includes a discharge control switch connected to the battery for cutting off a discharge current of the battery in response to a discharge stop signal. A control circuit is connected to the battery and the discharge control switch generates the discharge stop signal for deactivating the discharge control switch when a voltage of at least one cell reaches a lower limit. The control circuit includes a switch holding circuit for continuously supplying the discharge stop signal to the discharge control switch for a predetermined time after the discharge stop signal is generated regardless of the cell voltage.

Abstract: An MR head includes a slider, and a film structure part which is located on an air outflow side of the slider and includes an MR element for reproducing. The film structure part has an end surface located on an identical side as a floating surface of the slider. The end surface of the film structure part and the floating surface of the slider form a step-like recess which has a depth making it possible to prevent a fine projection on a magnetic disk from hitting the end surface of the film structure part.

Abstract: A burst mode optical transmitter circuit comprises a semiconductor laser, a photodiode for monitoring the light output from the semiconductor laser, a current-voltage converting circuit for converting the current detected by the photodiode into a voltage, an APC amplifier, a holding circuit for holding, as a current control signal, the output signal from the APC amplifier, a driving circuit for supplying a driving current to the semiconductor laser according the current control signal from the holding circuit and the the data input in the burst mode, and a data interruption detecting circuit for detecting an interrupt period of the data input to the driving circuit to reset the holding circuit, in which the current control signal held in the hold circuit is reset by the reset signal, whereby a stable burst optical transmission can be performed stably with a simple construction.

Abstract: In a wavelength multiplexing light source used in an optical wavelength division multiplexing (WDM) transmission system and the like, at least three semiconductor lasers of single longitudinal mode have oscillation frequencies outside of their pull-in range at a normal injection locking without a modulation side band, an output light of a first semiconductor laser is injected in one way into a second semiconductor laser having an oscillation frequency adjacent to that of the first o semiconductor laser through a first one-way optical injection means to generate a modulation side band. The output light of the second semiconductor laser is then injected in one way into a third semiconductor laser having an oscillation frequency adjacent to that of the second semiconductor laser through a second one-way optical injection means to generate the modulation side band for an injection locking.

Abstract: Disclosed is an ATM switching apparatus capable of reducing a probability an IAM acceptance being rejected due to a difference in bandwidth acquiring algorithm. The ATM switching apparatus is constructed such that when receiving an IAR due to the difference in bandwidth calculation algorithm for the IAM indicating a use of a certain VPC, a calculated bandwidth value is set in an estimated free bandwidth value about the VPC within a bandwidth management table, a value given by Calculation Bandwidth Value/Free bandwidth Value is set in a ratio, and the VPC is selected by using not the free bandwidth value but the estimated free bandwidth value (=Free Bandwidth Value×Ratio) when transmitting the IAM. It is another contrivance that when the free bandwidth value changes, the estimated free bandwidth value is also changed to establish “Estimated Free Bandwidth Value=Free Bandwidth Value×Ratio” without changing the ratio.

Abstract: A device for generating a Gantt chart made up of at least one schedule bar includes, a display showing the Gantt chart, an input unit receiving input to point at a position on the display, a Gantt-chart-generation processing unit generating a schedule bar having a start point and an end point by setting the start point at a first position indicated by the input unit and setting the end point at a second position indicated by the input unit, and a work-step-division processing unit dividing the schedule bar into a plurality of work steps at a plurality of third positions indicated by the input unit.

Abstract: A transmission system for transmitting a data signal with an analog passband signal through a analog transmission line. The data signal is transformed to a signal representing a descrete data signal point in a vector signal space. The analog passband signal is transformed to a base band signal, and the base band signal is superimposed on the signal representing a descrete data signal point. A signal representing the superimposed data signal point is modulated and transmitted through the analog transmission line. In a receiver, the data signal point is decided from the signal representing the superimposed data signal point, and the superimposed base band signal is extracted by subtracting the decided result from the signal representing the superimposed data signal point. The base band signal is transformed to the analog passband signal. A portion of information carried by the analog passband signal may be converted to a digital signal, and the digital signal is multiplexed with the data signal.

Abstract: A processing apparatus for measuring accumulated values of performance monitoring (PM) parameters concerning a reception signal received by a transmission device, which is capable of detecting upper layer failures in a more accurate, hardware-based way, without increasing the workload imposed on the system's firmware. PM parameters represent the statistics of events that meet prescribed criteria for defects and anomalies in the reception signal. The processing apparatus has a plurality of failure detection units to detect different kinds of failures in the reception signal and produce failure detection signals corresponding thereto. Those failure detection units include a first failure detection unit that detects a first kind of failure and a second failure detection unit that detects a second kind of failure. On the basis of the failure detection signals, a PM controller detects at least one kind of PM parameter, and a counter unit accumulates the detected PM parameter.

Abstract: An optical communication system having a transmitting station for outputting WDM(wavelength-division multiplexing) signal light, an optical fiber transmission line, a receiving station, and an optical repeater including an optical amplifier. The transmitting station includes a supervisory circuit for detecting the number of channels of the WDM signal light and transmitting supervisory information including the number of channels to the optical repeater. The optical repeater further includes a circuit for controlling the optical amplifier so that the output level of the optical amplifier becomes a target level. The target level is set according to the supervisory information. According to the structure, it can be possible to provide a system which can easily respond to a change in the number of WDM channels.

Abstract: A frequency modulation method and modem unit for a frequency modulation using a common filter which uses a large number of carrier frequencies include a frequency-shifting unit for subjecting an input data to a frequency shift corresponding to a binary data value, a filter for limiting an output obtained by the frequency-shifting unit to a common band, and a modulation unit for frequency-modulating an output obtained by the filter, by a carrier frequency having an intermediate value of the frequencies respectively corresponding to the binary data values.

Abstract: An electronic transaction terminal, in which a memory for information for storing therein an identification number inputted from a ten-key and a power unit for memory for supplying power to this memory for information are connected to each other with a film for printed pattern wiring (FPC). The FPC is placed throughout the internal surface of a security case. If someone tries to make a hole on the security case, any point of the wiring pattern of the FPC is cut off. For this reason, power supply to the memory for information is shut down and data on the memory for information is deleted.

Abstract: A liquid crystal display device includes a first substrate and a second substrate sandwiching a liquid crystal layer therebetween, a first polarizer disposed adjacent to the first substrate at a side opposite to a side of the first polarizer facing the liquid crystal layer, with a first gap between the first polarizer and the first substrate, a second polarizer disposed adjacent to the second substrate at a side opposite to a side of the second polarizer facing the liquid crystal layer, with a second gap between the second polarizer and the second substrate, wherein at least one of the first and second gaps includes therein a first retardation film having a positive optical anisotropy and a second retardation film having a negative optical anisotropy, such that the first retardation film is disposed closer to the liquid crystal layer with respect to the second retardation film.

Abstract: A time correcting method includes steps of receiving notifying information from a base station, the notifying information including an identification number identifying the base station, selecting a time differential information item corresponding to the identification number from a table which indicates a relationship between identification numbers identifying base stations and time differential information items in service areas of the respective base stations, and correcting a present time using the selected time differential information item.

Abstract: A method and apparatus for interframe predictive video coding and decoding which avoid the accumulation of rounding errors and thus obtain high-quality reproduced pictures. A frame memory outputs at least one reference picture to a prediction picture calculation unit, according to motion vector information with half-pel accuracy. From the reference picture(s), the prediction picture calculation unit produces a prediction picture by performing interpolation operations if the motion vector has a half-pel component. Here, each interpolated pel value is rounded off to an integer according to a particular rounding algorithm specified by a calculation controller. More specifically, the prediction picture calculation unit supports a first algorithm that rounds off the pel values toward positive infinity and a second algorithm that rounds off them toward negative infinity.