Abstract: A liquid crystal display device includes a first substrate and a second substrate sandwiching a liquid crystal layer therebetween, a first polarizer disposed adjacent to the first substrate at a side opposite to a side of the first polarizer facing the liquid crystal layer, with a first gap between the first polarizer and the first substrate, a second polarizer disposed adjacent to the second substrate at a side opposite to a side of the second polarizer facing the liquid crystal layer, with a second gap between the second polarizer and the second substrate, wherein at least one of the first and second gaps includes therein a first retardation film having a positive optical anisotropy and a second retardation film having a negative optical anisotropy, such that the first retardation film is disposed closer to the liquid crystal layer with respect to the second retardation film.
Abstract: Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.
Type:
Grant
Filed:
September 16, 1999
Date of Patent:
August 28, 2001
Assignee:
Fujitsu Limited
Inventors:
Mark Thomas McCormack, Hunt Hang Jiang, Solomon I. Beilin, Albert Wong Chan, Yasuhito Takahashi
Abstract: An electronic circuit module has an electronic circuit module main body and two signal pedestals, one on each side of the main body. The first signal pedestal is formed at a level higher than the second signal pedestal by an amount equal to the vertical thickness of the second signal pedestal. Signal lines are formed on a bottom surface of the first signal pedestal and on a top surface of the second signal pedestal. When connected to adjacent electronic circuit modules, the first signal pedestal of the electronic circuit module overlaps a second signal pedestal of one adjacent electronic circuit module, and the second signal pedestal underlaps a first signal pedestal of another adjacent electronic circuit module to electrically connect electronic circuit modules in multiple stages, improving signal connections and reducing the size of the electronic circuit module package.
Abstract: A quantum semiconductor memory device includes a quantum structure formed on a substrate, wherein the quantum structure includes a plurality of self-organized quantum dots forming a strained heteroepitaxial system with respect to the substrate and an accumulation layer formed adjacent to the self-organized quantum dots, and wherein the self-organized quantum dots are formed of a semiconductor crystal having a composition set such that quantum levels of the self-organized quantum dots are located higher than a conduction band of the accumulation layer.
Abstract: A semiconductor device test board for performing a test on a semiconductor device includes a supporting board formed of an insulating material and contact parts which are formed on the supporting board, and which can be connected to solder bumps formed on a semiconductor device to be tested. Each of the contact parts includes contact base layers formed of conductive materials other than solder and a solder layer having a thin-film shape, and covering the contact base layers.
Abstract: A semiconductor device includes cell areas laid out along a periphery of the device. A plurality of transistors are formed in each cell area, and are separated into at least three transistor groups arranged in a direction perpendicular to a circumferential direction of the semiconductor device. Each transistor group is connected to a high-potential power supply or a low-potential power supply. The semiconductor device has at least one interconnection line common to both the transistor group connected to the high-potential power supply and the transistor group connected to the low-potential power supply. The interconnection line serves to connect those transistor groups to external pads.
Abstract: A face up BGA package has a plurality of terminals and lead pads on a package substrate. Connecting some of the terminals to their corresponding lead pads via nonconnection terminals when changing the size of a chip mounted on the package substrate makes it possible to connect all necessary terminals and lead pads by using inner leads without short circuiting the inner leads and without shortage of space in which to wire the inner leads.
Abstract: A signal processing apparatus having a register unit with the number of bits required for signal processing, which is not larger than predetermined number of bits, and comprising a ROM which inputs, as an address signal, an output signal from the register unit or an input signal to the signal processing apparatus, and uses an input signal to the register unit as a part of an output signal from the ROM. This makes it possible to greatly reduce the cost of a system which executes complex processing yet requires a reduced number of bits in the input signals and a reduced number of bits for the register that is essentially required by reducing the amount of signal processing and the number of electric components, to greatly improve the quality of the apparatus accompanying the reduction in the number of electric components, and to cheaply increase the signal processing functions without decreasing the processing speed.
Abstract: In a magnetic sensor, a lower terminal layer, a magnetosensitive layer, and a cover film are simultaneously patterned into substantially the same size. The opposing surface of the lower terminal layer, which opposes the magnetosensitive film is substantially superposed on one opposing surface of the magnetosensitive film. The opposing surface of the upper terminal layer, which opposes the magnetosensitive film is formed into a shape smaller than and included in the other opposing surface of the magnetosensitive film. This implements a magnetic sensor which uses a CPP structure and is yet readily processible and which includes a substantially accurate fine CPP structure in accordance with a desired output.
Abstract: A disk drive includes a housing having a base and a cover fixed to the cover, a disk rotatably mounted in the housing and having a plurality of tracks, a head for reading/writing data on the disk, and an actuator for moving the head across the tracks of the disk. The cover is composed of a molded resin and a metal sheet integrally embedded in the molded resin.
Abstract: A ring transmission system includes a plurality of nodes that are connected to each other to form a ring by a bi-directional line switched ring (BLSR) method.
Abstract: The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42.
Abstract: An apparatus for correcting a bar width comprises a detecting section calculating a reference bar width serving as a reference of bar widths, a first calculation section calculating an average value of a plurality of reference bar widths, a second calculation section calculating an error value between a bar width of a bar to be corrected and the reference bar width calculated by the detecting section, and a correcting section correcting the bar width of the bar to be corrected by using the calculated average value when the calculated error value is not less than a predetermined value.
Abstract: A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.
Abstract: According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line.
Abstract: A magnetic sensor which includes a laminate comprising a first magnetic layer of soft ferromagnetic material, a nonmagnetic layer, a second magnetic layer of ferromagnetic material, and an antiferromagnetic layer, and a converting element for detecting the change in external magnetic field as the change in resistance and outputing it, with at least part of the first magnetic layer being formed of an Ni—Fe material, and the content of Ni, xNi, in wt % and the thickness, t, in nanometer thereof satisfying the relation represented by the following equation: 1 x N1 ≧ - B 1 Surf + B 1 Bulk · t B 2 Surf + B 2 Bulk · t
Type:
Application
Filed:
January 11, 2001
Publication date:
August 23, 2001
Applicant:
FUJITSU LIMITED
Inventors:
Lajos Varga, Yutaka Shimizu, Shin Eguchi, Atsushi Tanaka
Abstract: A magnetic head having an accurately defined minute core width is provided. The magnetic head comprises a pair of soft-magnetic poles which are located adjacent to a magnetic disk and opposed to and apart from each other with a predetermined distance along a predetermined direction, and generates a magnetic field therebetween to magnetize the magnetic disk, wherein the upper magnetic pole 3 of the two magnetic poles has, at one end which is adjacent to the magnetic disk, a tip of a block form that has a front wall which is adjacent to the magnetic disk and a pair of side walls which extend in a direction perpendicular to the front wall as well as in the above-described predetermined direction, with the tip having an upper non-magnetic regions 3—2 which has been formed by demagnetization by introducing impurity through each of the two side walls to a predetermined depth.
Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.
Abstract: A delay time adjusting circuit adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The circuit comprises first dividing means for dividing a frequency of the input signal by a first frequency division rate; delaying means for delaying the input signal by a predetermined time; second dividing means for dividing a frequency of the input signal delayed by the delaying means by a second frequency division rate; comparing means for comparing a phase of a signal generated by the first dividing means and a phase of a signal generated by the second dividing means; and adjusting means for adjusting the predetermined time according to a comparison result obtained by the comparing means.
Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.