Patents Assigned to Fujitsu
  • Publication number: 20010016440
    Abstract: It is an object to reduce a load given to connectors when the connectors are connected with each other in a connection mechanism composed of the main body side connector 20 and the base unit side connector 10 in which contact terminals of both the connectors are contacted with each other when the connectors are moved in the mutual direction. The base unit side contact terminal 12 is movably attached to the housing 11 of the base unit 10 so that the base unit side contact terminal 12 can be located at a non-contact position with respect to the contact terminal 22 of the main body side connector 20 at the first stage of engagement between the connectors 10, 20 and so that the base unit side contact terminal 12 can be located at a contact position with respect to the main body side connector 20 at the latter stage of engagement between the connectors 10, 20.
    Type: Application
    Filed: March 26, 2001
    Publication date: August 23, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Masao Katsuta
  • Publication number: 20010015932
    Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
    Type: Application
    Filed: April 12, 2001
    Publication date: August 23, 2001
    Applicant: Fujitsu Limited
    Inventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi kawashima, Minoru Yamashita, Shouichi Kawamura
  • Publication number: 20010016871
    Abstract: The present invention provides a distributed processing system that eliminates the need for server clustering technology and will not pose a problem that the overall system would go down when the server fails, and clients for use in said system.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Shigeru Fujita
  • Publication number: 20010015926
    Abstract: The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal. The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.
    Type: Application
    Filed: February 16, 2001
    Publication date: August 23, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiharu Kato, Satoru Kawamoto
  • Patent number: 6277718
    Abstract: The method for fabricating a semiconductor device comprises an insulation film forming step of forming an insulation film 12 on a semiconductor substrate 10, a semiconductor layer forming step of forming a semiconductor layer 14 on the insulation film 12, and an impurity implanting step of implanting an impurity containing hydrogen into the semiconductor layer 14, the method being characterized by further comprising a fluorine implanting step of implanting fluorine in at least the insulation film 12. The dangling bonds of the insulation film can be bonded with the fluorine, whereby the fluorine, which has higher bonding energy with respect to silicon of the insulation film than hydrogen, is never dissociated from the silicon of the insulation film in the following heat treatments, BT stress test, etc. Accordingly, an interface state density in the interface between the insulation film and the semiconductor substrate can be depressed low, and a fixed charge in the insulation film can be depressed small.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Naganuma, Shinji Sugatani
  • Patent number: 6278864
    Abstract: A compact low-power radio frequency (RF) transceiver with a built-in antenna provides wireless communication between a computer and another device. A direct conversion receiver together with a voltage controlled oscillator, phase lock loop circuits, digitally controlled divider circuits and a patch antenna are packaged into a compact enclosure, having dimensions within the PCMCIA format. In some embodiments, the transceiver enters a sleep mode whenever it is idle in order to further conserve power. In other embodiments, a signature detector enables the transceiver to distinguish between noise and valid messages by recognizing a signature word embedded in the data packet.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited (Japan)
    Inventors: James D. Cummins, Bradley E. Thomson, William F. Kern, Duong X. Dinh
  • Patent number: 6278141
    Abstract: An enhancement-mode semiconductor device includes a barrier layer formed on a channel layer and a gate electrode provided on the barrier layer, wherein the gate electrode is formed with an orientation chosen so as to maximize a threshold voltage of the semiconductor device.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Eizo Mitani, Hiroyuki Oguri
  • Patent number: 6278647
    Abstract: Connections of global data buses GDB0 and GDB1 to local data buses LDB00 to LDB04 in a bank 1 are reverse to those in a bank 0. That is, the global data bus GDB0 is connected to every other local data bus LDB00, LDB02 and LDB04 including both sides in the bank 0, and to every other local data buses LDB11 and LDB13 excluding both sides in the bank 1, while the global data bus GDB1 is connected to every other local data buses LDB01 and LDB03 excluding both sides in the bank 0, and to every other local data bus LDB10, LDB12 and LDB14 including both sides.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoru Saitoh, Shinichi Yamada, Masato Takita
  • Patent number: 6279006
    Abstract: A structured data management system capable of easily changing the definition of a logical structure and controlling semantics described in data adapted to the defined structure as intended by persons who have defined the logical structure. A contents model defines an internal structure of a contents description. The contents description describes data to be managed according to the contents model. An operation description is coupled to the contents model and manipulates data in the contents description depending on the structure of the data in the contents description. The operation description functions to define semantics of each element of the structure defined by the contents model. An operation description executing unit executes the operation description coupled to the contents model. A structure managing unit verifies and manages the structure of the contents description according to the contents model.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Nobuhisa Shigemi, Hiroyuki Yamamoto, Gengo Tazaki, Makoto Yoshioka, Mitsuhiro Kokubun
  • Patent number: 6278539
    Abstract: An optical modulator having a voltage—optical output characteristic in which optical output varies periodically with respect to a voltage value of an electrical drive signal is driven by a modulator driving voltage signal, which has an amplitude of 2·V&pgr; between two light-emission culminations or two light extinction culminations of the voltage—optical output characteristic. A low-frequency superimposing unit superimposes a prescribed low-frequency signal on the modulator driving voltage signal, and an operating-point controller controls the operating point of the optical modulator by detecting operating-point drift of the optical modulator based upon the low-frequency signal component contained in an optical signal output from the optical modulator and controlling the bias voltage of the optical modulator in dependence upon the drift of the operating point of the optical modulator.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroki Ooi, Hiroshi Nakamoto, George Ishikawa, Takuji Yamamoto, Yoshinori Nishizawa
  • Patent number: 6277734
    Abstract: A semiconductor device fabrication method comprises the steps of forming on a substrate 10 a plurality of lines 20 on upper surfaces and side surfaces of which a first insulation film is formed on; depositing a second insulation film 28 on and/or above the substrate 10 and the lines 20, filling gaps between one of the lines 20 and its adjacent one to thereby form the second insulation film 28; forming on the second insulation film 28 a third insulation film 30 having etching characteristics different from those of the second insulation film 28; etching the third insulation film 30 with the second insulation film 28 as a stopper; and etching the second insulation film 28 to a contact hole 32 which reaches the substrate 10.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventor: Takahiko Mizutani
  • Patent number: 6278422
    Abstract: In a method of driving a plasma display panel to display gradation, a field includes a plurality of subfields, the subfields of each field are separated into a plurality of subfield groups, and each subfield is weighted in brightness in such a manner that the subfields in the subfield group are all equal in weight. An address period and a sustain period are allocated to each subfield. In at least one subfield group, a number of times of sustaining discharge for a subfield to be sustained independently is set different from a number of times of sustaining discharge for at least one other subfield.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Ukai, Hitoshi Hirakawa
  • Patent number: 6278984
    Abstract: A vendor ID is written to a system area of a write-once optical disk. When the write-once optical disk is loaded onto a write-once disk drive, a control CPU reads the vendor ID. The vendor ID is written into the header of software received through an interface unit. When the software is input to an SD circuit, the control CPU reads the vendor ID. The control CPU compares the vendor ID in the system area of the write-once optical disk with the vendor ID of the header of the software and checks whether or not the two IDs are identical. If the two IDs correspond to each other, the control CPU writes the software to the write-once optical disk.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoshi Itami, Kazuo Nakashima, Kenichi Utsumi
  • Patent number: 6279104
    Abstract: A debugging system for use with a data parallel processing apparatus is disclosed. Sequential debuggers debug a plurality of parallel processes. The processed result is output as reply information to a management processor. The management processor knows the reason why it has received reply information and manages debugging statuses of the individual sequential debuggers corresponding to the reply information against the debug command.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Yuji Sato, Norihisa Murayama
  • Patent number: 6279152
    Abstract: When a processing unit of a vector computer detects an optimization directive line for optimizing a list accessing method during the compilation, an access method is automatically changed according to an instruction of the directive line. For example, data to be accessed are copied to a work array, the access order is changed at random, and a scalar load process is performed. As a result, high-speed list access can be realized without a bank conflict at a vectorization.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaki Aoki, Masahito Morishima
  • Patent number: 6278609
    Abstract: An electronic device having an IC card slot into which an IC card is removably inserted. The IC card slot has a slot side connector to which a card side connector of the IC card is electrically connected and a socket formed in an approximately U-shaped. The slot side connector is mounted on a bottom portion of the socket. Guide grooves for guiding side edge portions of the IC cards are formed in an inner surface portion of each of guide rail portions formed on both sides of the socket, and a plurality of heat radiation fins are formed on an outer surface portion of each guide rail portion. The socket is made of a metal material having a high thermal conductivity. Heat generated from the IC card is radiated via the guide rail portions and the heat radiation fins.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Masumi Suzuki, Akira Ueda
  • Patent number: 6278421
    Abstract: In a plasma display apparatus with power consumption control, a control method is provided that eliminates unnaturalness of images during power control and that holds power consumption to within a target value regardless of the type of image pattern displayed. Differences between power consumption PSA and target value PSET are summed to calculate power consumption sum value PSUM, and if PSUM is negative, brightness set value MCBC is set to its maximum value MCBCMAX. If PSUM is positive, the value calculated by the equation “MCBCMAX−PSUM×MCBCMAX/PSUM,MAX” is set as the MCBC.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Katsuhiro Ishida, Hiroyuki Wakayama, Hirohito Kuriyama, Akira Yamamoto, Ayahito Kojima, Masaya Tajima, Kyoji Kariya
  • Patent number: 6278536
    Abstract: This invention discloses an optical transmission device used for bi-directional optical communications. The optical transmission device comprises a uni-directional optical signal processing unit for performing specified optical signal processing for optical signals transmitted in a single direction and a uni-direction/bi-direction changing unit for unifying the flows of clockwise and counterclockwise optical signals in a single direction, inputting these flow-unified optical signals to the uni-directional optical signal processing unit and dividing the flow of optical signals from the uni-directional optical signal processing unit between clockwise and counterclockwise directions. Bi-directional wavelength-division multiplexing optical communications can be performed by unifying the transmission routes (flows) of optical signals transmitted in two ways in a single direction and using the existing optical transmission device for uni-directional optical communications.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Yutaka Kai, Terumi Chikama
  • Patent number: 6278219
    Abstract: A surface acoustic wave device which reflects a surface acoustic wave is provided. The reflector of the surface acoustic wave device includes electrode fingers. The electrode fingers are disposed at predetermined intervals d, and are divided into five groups by the width. The widths w of the electrode fingers are varied between widths w1, w2, and w3, so that the reflectance becomes similar to the Hamming function.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Yasufumi Kaneda, Jun Tsutsumi, Kenya Hashimoto, Tatsuya Omori, Motoyuki Tajima, Masatsune Yamaguchi
  • Patent number: D446789
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Toru Watanabe, Takeshi Ohwe