Abstract: A semiconductor inspection apparatus performs a test on a to-be-inspected device which has a spherical connection terminal. This apparatus includes a conductor layer formed on a supporting film. The conductor layer has a connection portion. The spherical connection terminal is connected to the connection portion. At least a shape of the connection portion is changeable. The apparatus further includes a shock absorbing member, made of an elastically deformable and insulating material, for at least supporting the connection portion.
Abstract: A cooling device of a laser diode array includes a stacking of a plurality of metal plate members formed with a branched groove pattern or apertures acting as a cooling water path, by a chemical etching process.
Abstract: A decoder circuit has two separate portions, a low voltage portion and a high voltage portion. Through the use of the high voltage portion, the decoder circuit is capable of supplying high program voltage. Through the use of low voltage portion and isolated from the high voltage portion, quick read operation is performed.
Abstract: A lens assembly is provided for causing a laser beam to form a focal spot in a recording region of an optical recording medium including a substrate. The lens assembly includes a plurality of focusing lenses each including an incidence surface for receiving the laser beam and an emitting surface for emitting the laser beam. Each focusing lens is arranged so that the emitted laser beam is caused to converge at a first focus located in contact with the substrate of the optical recording medium. The focusing lens is also arranged so that light sent from the first focus is caused to converge at a second focus located in the recording region of the optical recording medium to form the focal spot.
Abstract: A multi-function unit includes a printer engine, a logical copying machine carrying out a copying process with respect to a recording medium by the printer engine, and a plurality of logical printers carrying out printing processes with respect to the recording medium by the printer engine. The logical copying machine and the logical printers carry out apparent parallel operations.
Abstract: Disclosed herein is an optical filter usable as an optical add/drop circuit. The optical filter includes a first port, an optical filter member having a characteristic changing according to a position in a predetermined direction, a second port optically coupled to the first port by a transmitted light path concerning the optical filter member, a reflecting unit optically coupled to the first port by a reflected light path concerning the optical filter member, and a mechanism for displacing the optical filter member in the above predetermined direction. With this configuration, a variable pass band or a variable stop band can be obtained, and the characteristic is stable.
Abstract: An ATM exchange system which handles fixed-length cells, such as an ATM exchange, is designed in such a manner that even when a failure occurs particularly in an interface unit or an ATM switch section, downstream stations can be informed of the failure reliably and that when some failure is detected, counting of a charge counter is disabled to always ensure proper charging.
Type:
Grant
Filed:
December 24, 1996
Date of Patent:
June 12, 2001
Assignee:
Fujitsu Limited
Inventors:
Yoshihiro Watanabe, Hiroshi Nishida, Sumie Morita, Kenichi Okabe
Abstract: A LAN terminal equipment comprises a plurality of slots, each capable of accommodating a LAN control board, at least one ROM socket capable of holding a MAC ROM, and an input/output control unit. The input/output control unit determines a correspondence between the LAN control board and the MAC ROM, thereby ensuring the uniqueness of MAC address and also making a primary/spare dual configuration possible.
Abstract: A polarization device includes a reflection-type polarization element disposed at a side to which an optical beam comes in and an absorption-type polarization element disposed behind the reflection-type polarization element, wherein the reflection-type polarization element and the absorption-type polarization element are disposed such that a transmission axis of the reflection-type polarization element coincides with the transmission axis of the absorption-type polarization element. Further, an optical projector using such a polarization device is disclosed.
Abstract: An integrated communication system for voice and data connecting an Ethernet LAN to an external communication network by utilizing a conventional communication system. An interface connected to the Ethernet LAN and transferring a voice signal at a data link level without processors is stored in a personal computer. An ISDN voice interface for connecting the personal computer to the external communication network with a voice channel is connected to the LAN. The input/output data of the ISDN voice interface and various routers performing data communication on the LAN is multiplexed/demultiplexed in a plurality of channels by an ADSL multiplexer. The input/output data of the multiplexer is connected to the external communication network through an access network having a user interface.
Abstract: A FIFO circuit with a reduced number of buffers connected to output ports and thereby lowering parasitic capacitance. The FIFO circuit includes an input register for storing data therein supplied from a plurality of input ports. A shifter rearranges the data supplied from the input register and a shift register stores therein and shifts the data supplied from the shifter. A selector circuit selects either the data from the input register or the data from the shift register such that valid data fill places from a least significant side of the output ports. A control circuit controls the input register, the shift register, the shifter, and the selector circuit.
Abstract: The present invention discloses a function extending apparatus detachably connected to an electronic apparatus to enhance functions of the electronic apparatus, the function extending apparatus including a connection control part controlling a connection between a battery and a charging part in accordance with a result of detection of docking to the electronic apparatus so as to supply power from the electronic apparatus to the battery.
Abstract: A method and apparatus for generating external power wiring layout data for a semiconductor integrated circuit device determines an optimum layout without performing time consuming circuit simulation. An external power wiring supplies power to each of the functional blocks of the device. Design information is used to calculate a current consumption ratio for each power supply terminal of each functional block. Then, the current consumption for each power supply terminal is calculated using the calculated current consumption ratios. An external power wiring network is generated based on the calculated current consumption for each terminal. The generated external power wiring network is then analyzed and voltage and current values for each part of the network are calculated. Using the calculated voltage and current values, the wires are then optimally sized.
Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
Abstract: There is provided a non-volatile memory circuit which stores information by altering a threshold voltage of memory cells so as to associate first and second threshold voltages respectively with first and second data values, and which has a first recorded state and a second recorded state different from the first recorded state such that in the first recorded state, the first and second threshold voltages are lower or higher than a first reference voltage, and in the second recorded state, the first and second threshold voltages are lower or higher than a second reference voltage different from the first reference voltage. The first or second reference voltage is set in accordance with the first and second recorded states. With the above structure, in the first recorded state, the first and second threshold voltages are either lower or higher than the first reference voltage within a voltage range lower or higher than the second reference voltage.
Abstract: A storage capacitance Cs0 (=Cs+Csadd) added to a pixel capacitance is set such that a transmittance T1 at a voltage V1 of a pixel electrode becomes substantially equal to a transmittance T2 at a voltage V2 of the pixel electrode when a holding period is terminated. In the case of a normally black type liquid crystal display device, for example, when it is assumed that a white data voltage is VdW, a liquid crystal capacitance in white display is ClcW, and a liquid crystal capacitance in black display is ClcB, a capacitance value of the storage capacitance Cs0 is set such that difference between the transmittance obtained at the pixel voltage, that is changed by an amount of variation &Dgr;Vs of a pixel voltage expressed by &Dgr;Vs=VdW ((ClcW−ClcB)/ (ClcW+Cs0)), and the transmittance obtained at the white data voltage VdW can be reduced smaller than 13% of the transmittance obtained at the white data voltage VdW.
Abstract: FETs 31 to 34 for amplification are connected between an input transmission line 10 and an output transmission line 20. A terminating circuit 29 having a capacitor 292 and a terminating resistor 291 connected in series is connected to an end of the output transmission line 20. To improve a flatness of the gain over a low frequency band, a series-connected circuit having a capacitor 71 and a resistor 61 between the gate of each FET and ground, wherein the design parameter of this circuit is determined so that the impedance thereof is lower in the low frequency band but higher in a high frequency band than the input impedance of each FET.
Abstract: A reference voltage generator circuit generates a stable reference voltage that may be used by other circuits, such as an A/D converter and a D/A converter. The reference voltage generator circuit includes a rough resistor bank having a pair of first resistors connected in series between a low potential reference voltage and a high potential reference voltage. A first fine resistor bank is connected in shunt with one of the resistors in the rough resistor bank and a second fine resistor bank is also connected in shunt with the same resistor in the rough resistor bank. Switches are connected between nodes between the resistors in the fine resistor banks and another circuit or system, such as an A/D converter.
Abstract: In order to measure a scanning light cut-off region, an output of a light receiving element and a threshold value set by an MPU are compared by a comparator and a region where the former is smaller than the latter is measured as the scanning light cut-off region. During one cycle of optical scanning, this threshold value is switched in a plurality of stages according to the scanning angle. By accurately measuring the scanning light cut-off region, the correct position and size of an indicator such as a finger or pen are calculated.
Abstract: A method of generating test data for conducting a test of an LSI circuit generates the test data based on a model of the LSI circuit that has a processor therein operating based on a micro-program. The method includes the steps of ROM-modeling the micro-program which is already debugged during logic simulation that determines logic design of the LSI circuit, and debugging the micro-program and the LSI circuit by carrying out said test of an LSI circuit on the model of the LSI circuit.