Abstract: A work conveying and transferring apparatus has a trolley having a casing defining a hermetically sealed space, and a support portion provided on the trolley for placing at least one container containing a cassette carrying works. A container opening device is provided on the trolley to open the container placed on the support portion, and a cassette transferring device is provided for transferring the cassette from the trolley to a treating apparatus, with the container placed on the support portion opened. The support portion is provided in the sealed space, and works can be double sealed by the sealed space and the container.

Abstract: The invention provides a virus extermination method by which an error in operation by a user is prevented and optimum virus extermination based on a type of a virus can be performed without imposing much burden in operation.

Abstract: A field insulating film defines a plurality of active regions disposed regularly in terms of two dimension on the surface of a semiconductor substrate. Each active region includes one bit contact region and subsidiary active regions extending from the bit contact region in four directions. A plurality of first word lines are formed which extend as a whole in a first direction on the semiconductor substrate, and a plurality of second word lines are formed which extend as a whole in a second direction on the semiconductor substrate, crossing the first word lines. Two subsidiary active regions cross the first word lines and remaining two subsidiary active regions cross the second word lines. A plurality of bit lines are formed which extend as a whole in the first and second directions on the semiconductor substrate, crossing each other. Each bit contact region is connected to a corresponding one of the bit lines. Four transistors share one bit contact, and these four transistors have different word lines.

Abstract: A memory control system employing at least one clock synchronous memory which is controlled by a memory control unit includes an interface circuit. The interface circuit functions as an output buffer synchronous with a clock. Thus, the interface circuit holds a memory control signal, which is output from the memory control unit for controlling the memory, and transmits the memory control signal to the memory in the predetermined time. In this configuration, access to the memory is made in consideration of the delay time required for a memory control signal to reach the memory via the interface circuit. Preferably, the presence or absence of the interface circuit for holding a memory control signal is determined based on an operation mode in which the memory control unit is established. Further proposed is a memory control method for controlling at least one clock synchronous memory which is implemented in the memory control system.

Abstract: A high speed address sequencer allows for a generation of address signals using a clock with higher frequency. The high speed address sequencer can be used in many semiconductor devices, especially in flash memory devices. By reducing a number of gate delays, the high speed address sequencer can generate all address signals in a reduced time period. By using an address signal as a clock for generation of some of the other address signals, the high speed address sequencer is allowed more time to generate all address signals with a given clock frequency. The reduction in the number of gate delays can be combined with the use of the address signal as a clock.

Abstract: The semiconductor device includes a substrate, a semiconductor component, and a cap covering the semiconductor component and attached to the substrate. The cap has a top wall, a plurality of side walls 14 extending downward from the top wall and a bottom wall. Opening are provided in the side walls of the cap at corners thereof. Due to the provision of openings, the cap can be manufactured without deformation thereof. Air or liquid can flow into, or out of, the interior of the cap, after the semiconductor deviced is completed.

Abstract: A finite impulse response circuit includes a delay line having a plurality of taps, receiving an input signal, a multiplying part for multiplying coefficients to signals obtained from the taps and adding multiplied results, and a shaping part for shaping the input signal by adjusting the coefficients. The shaping part includes a first tap coefficient setting circuit for correcting a signal distortion which is asymmetrical to right and left with respect to a signal point, and a second tap coefficient setting circuit for correcting a signal distortion which is symmetrical to the right and left with respect to the signal point. The first tap coefficient setting circuit sets the coefficient independently of the second tap coefficient setting circuit.

Abstract: A self-timing control circuit relating to the present invention comprises a clock cycle counting circuit for counting ocillation pulses during a period corresponding to a cycle of the master clock and generating a clock cycle count value. The count value for a period corresponding to the cycle of the master clock is calculated with this clock cycle counting circuit. The self-timing control circuit further comprises a control clock generating portion for generating the control clock, as timed by synchronizing with the master clock, starting a count of the oscillation pulses, and counting up to the clock cycle count value. As a result, the control clock generated is delayed from the master clock by the time taken to count to the measured count value. The timing of the control clock is delayed from the master clock by one cycle or an integer multiple thereof.

Abstract: An exchange constituting an ATM network administers the number of UBR connections for every line port included in the exchange. Upon receiving a request for setting a UBR connection, the exchange determines the route of the UBR connection on the basis of the number of the UBR connections administered for every line port included in the exchange.

Abstract: The present invention relates to a magnetic disk control unit which can accomplish active interchange of firmwares. Thus, in this invention, a firmware constituting the magnetic disk control unit includes an internal table area for retaining various data necessary for control, a save area for temporarily saving, of the data in the internal table area, data necessary before and after interchange of the firmware while the firmware undergoes active interchange, a first interruption control section serving, as interruption handling functions, a normal function to refer to the internal table area in accordance with an interruption for advancing to processing to the interruption and a busy response function to perform a busy response to the host unit during the firmware active-interchange, and a second interruption control section serving, as an interruption handling function, only a busy response function to accomplish a busy response to the host unit during the firmware active-interchange.

Abstract: A high temperature oxide superconductor is efficiently protected from the affects of water and acids by forming a passivation layer of a fluoride. The fluoride layer comprises a fluoride composed of one or more elements composing the oxide superconductor and/or one or more elements that can compose an oxide superconductor by replacing at least in part one or more elements composing the oxide superconductor.

Abstract: A communication support system includes a caller ID detection unit which detects a caller ID sent from a telephone network upon incoming of a call. A line switching unit switches on a first line between a voice signal path from a telephone set and a voice signal path from the telephone network before the connection between the telephone set and the telephone network is established. The line switching unit switches off the first line and switches on a second line between the voice signal path from the telephone set and a voice signal path from a data processing device after the caller ID is detected by the caller ID detection unit. The data processing device has a main control unit which retrieves a caller profile from a database in response to the caller ID detected by the caller ID detection unit, and transmits a. synthesized voice signal indicating the caller profile to the telephone set through the second line when the line switching unit switches on the second line.

Abstract: A method of forming a laminated glass substrate structure suitable for use in a display device or the like, includes the steps of: a) preparing a first glass substrate having first and second main faces; b) preparing a second glass substrate having third and fourth main faces; c) after the steps a) and b), adhering the first and second glass substrates with a space formed therebetween and with the third main face facing to the second main face; and d) after the step c), performing a smoothing process relative to all edges excepting one edge among edges defining the first main face. The laminated glass substrate structure provides an improved load resistance.

Abstract: The holding unit of a vacuum machining device is capable of preventing a work piece from being excessively heated and capable of stably machining the work piece. The holding unit comprises: a holder for holding a work piece; a pressing member for pinching the work piece with the holder; and a heat insulating member being provided to the holder, the heat insulating member contacting the work piece to restrict heat conduction thereto.

Abstract: High-accuracy position signals are obtained by correcting nonlinear position sensitivities of two phase signals demodulated from two-phase servo information, into linear ones. A position sensitivity adjusting unit detects the signal level at the intersection of position signals N and Q having different phases by a predetermined track pitch which are demodulated from read signals of two-phase servo information buried and recorded in a disk medium and makes an adjustment of the gain of an AGC amplifier so that the intersection signal level coincides with a predetermined level. A sensitivity correcting unit corrects into linear position sensitivities the nonlinear position sensitivities approximated by sine functions or cosine functions relative to the actual track position X of the two position signals N and Q output from the AGC amplifier.

Abstract: A method of fabricating a semiconductor device includes a step of attaching a circuit substrate on a semiconductor wafer in alignment with each other, providing an electrical interconnection between the circuit substrate and semiconductor devices formed in the wafer, providing solder bumps on the circuit substrate, and dicing the semiconductor wafer together with the circuit substrate thereon along a scribe line.

Abstract: In a process for producing a thin-film device, a conducting layer composed of an anodically oxidizable metal is formed on a substrate and is etched to form gate bus lines and gate electrode having upper surfaces parallel to the substrate and inclined side surfaces. The gate bus lines and the gate electrodes are anodically oxidized, so that they include inner conducting portions and outer insulating oxide films covering the inner conducting portions. The outer insulating films prevent the bus lines from short circuiting, and the inclined side surfaces of the bus lines makes it possible to fabricate a dense wiring arrangement.

Abstract: A magnetic sensor utilizing a giant magnetoresistance (GMR) effect, wherein an insulation layer with a contact hole is formed on a lower terminal layer, a GMR layer is formed thereover on the region including the entire contact hole and at least the surrounding insulation layer, and an upper terminal layer is formed thereover. The sensor offers several advantages in that it is easy to manufacture and is compact, and has a high degree of resistance change.

Abstract: A demodulator with a cross polarization interference canceling function for canceling interference of cross polarization in the main polarization includes a demodulating unit for demodulating a baseband signal of the main polarization, a phase control unit which controls the phase of an interference signal, which is a baseband signal of cross polarization, based upon an error in the demodulated signal, and an interference cancellation unit which cancels an interference signal component from the demodulated signal of the main polarization.