Abstract: A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place the RAM in a write protect mode. If the RAM receives a write instruction from the microprocessor when the RAM is in the write protect mode, then an illegal condition is indicated and a nonmaskable interrupt is generated to allow the terminal to recover. When the RAM is in the write protect mode, signals from the microprocessor restore the RAM to its normal read/write mode.

Abstract: A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present routine, to a first register of a push down stack. In addition, the microcommand also pushes down one level the contents of all of the registers in the stack containing previously stored return addresses. Thus, a sequential return to unfinished routines or subroutines is provided. When the subroutine or hardware interrupt service routine is completed, a code in the address field enables the return address of the previously branched from or interrupted routine to be retrieved from the first register in the push down stack and to provide it as the address of the next instruction to be executed.

Abstract: A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

Abstract: An adjustable diameter pulley, particularly suitable for the belt tension adjustment in belt transmission system such as those used in serial printers, utilizing a central core having a tapered portion, a threaded cylindrical portion and also a plastic ring having external cylindrical surface and a central tapered opening. The opening receives the conical portion of the core and is provided with deep slits which allow its expansion. A second ring, screwed on the cylindrical portion of the core, causes the expansion of the plastic ring to vary.

Abstract: Apparatus and method for measurement of the activity of a central processing unit of a data processing system resulting from the execution of a program or series of programs. A value is initially entered in an arithmetic circuit. Each time an instruction is executed, a quantity related to the amount of activity required to execute the instruction is decremented from the arithmetic circuit. When value in the arithmetic circuit reaches zero, the operating system is notified and a decision whether to continue the program or initiate some other activity in the data processing unit is made. The usage of the machine is therefore determined by the number of times the arithmetic circuit has reached zero during the execution of a program and by the quantity remaining in the arithmetic circuit when execution of the program is complete. Provision is made for other measurement modes such as decrementing the quantity in the arithmetic circuit by a clock.

Abstract: A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit.

Abstract: A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts.

Abstract: A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished.

Abstract: Method and apparatus for filling polygons displayed by a color CRT monitor of a raster graphic system. A graphic controller produces control signals which control the mode of operation of the system, two of which are a fast polygon write, or fast-fill write, mode and a fast polygon display, or display fast-fill, mode. When the system is in the fast polygon write mode, the graphic controller reads fast-fill toggle bits from a frame memory of boundary pixels defining initial and terminal pixels of each fill element. The fast-fill toggle bits of boundary pixels are set if the toggle bit read from memory was not set and, if set, it will reset it. In the fast polygon display mode, the system senses the initial boundary pixel of each fill element by its fast-fill toggle bit being set and applies the color address of the initial boundary pixel to a color look-up memory until the terminal pixel of the fill element is read from the memory.

Abstract: A method for testing memory arrays embedded within electronic assemblies having other combinatorial logic elements connected to the inputs thereof. By following stated design rules, the embedded memory can be isolated from the combinatorial logic element and tested by use of a memory test subsystem either before or after the combinatorial logic elements are tested by a logic test subsystem. Both logic and memory tests are performed by a process that requires but a single handling of the electronic assemblies.

Abstract: Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.

Abstract: A printed circuit board interconnection system interconnects a pair of printed circuit boards in parallel planes so that all of the board components can be assembled in a standard fashion using standard connectors. The system includes an assembly having a spacer member positioned between the two circuit boards and a pair of ejector members which attach to each end of the spacer member. Each ejector member includes vertical and horizontal arm portions positioned to provide a predetermined mechanical advantage for separating the connectors mounted on each board as standard components.

Abstract: Each electronically operated customer installable/replaceable unit module of a computer system is separately packaged to totally enclose the electronic/mechanical parts of each module within a box-like container or wrapper, the structure designed to maximize air flow through the system. This includes an electronics base module containing the basic logic circuits for the system, a power module containing all of the systems power supply circuits, and a pair of storage modules each containing the electronics and mechanical parts of a diskette device. The modules are loosely inserted into comparably shaped opened compartments of an enclosure base and bezel assembly constructed for toolless installation and removal of modules. An enclosure top cover which fits into the bezel contains finger-like protrusions in addition to embossing. When latched to the base and bezel assembly, the top cover correctly positions and holds the modules in place.

Abstract: A continuous form for a printer, suitable for office automation, consists of: (A) a plurality of contiguous sheets identified by reference marks regularly spaced along the form length having sheets of a first type with a preprinted heading being followed at a preestablished frequency in the form by sheets of a second type, without such preprinted heading, so that, when used in a printer provided with a cutter, by printing on selected sheets of the form and by cutting the printed sheets from the form and by collecting the printed sheets, letters, circulars and similar paper on several sheets of equal size and different type can be automatically obtained, or (B) in an alternative embodiment, a plurality of identical contiguous sheets each comprising a preprinted head zone and a tail zone, both zones having the same height, the length of the sheets exceeding a desired final sheet length by the height of the tail zone, so that letters, circulars and similar papers on several sheets of equal size and different typ

Abstract: An interactive terminal data processing system includes a number of work stations, all coupled in common to a single conductor coaxial bus which may be up to one kilometer in length. Work stations may be connected to the bus by up to a ten foot coaxial cable with the connection to the bus being typically no less than thirty feet apart.

Abstract: A document holder attachable to a display terminal used to support one or more documents to be referenced by the display terminal user when information is entered or displayed on the display terminal screen is disclosed. The document holder is supported by an easel bracket which fits in an annular groove in the display terminal cover. The document easel is attached to the easel bracket such that an adjustment in the swivel or tilt of the display terminal for operator viewing convenience also results in a corresponding adjustment in the document holder such that the document holder always remains in the same relative viewing position with respect to the display terminal screen. The document holder can be easily added or removed from the display terminal and is reversible for either righthanded or lefthanded use.

Abstract: An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.