Patents Assigned to Hynix Semiconductor
  • Patent number: 8609491
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eui-Seong Hwang
  • Patent number: 8609535
    Abstract: A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Hee Jo, Sung Cheol Kim, Sung Min Kim
  • Patent number: 8609507
    Abstract: A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Kyung Kim, Min Sik Jang, Sung Deok Kim
  • Patent number: 8609544
    Abstract: A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Koo Lee
  • Patent number: 8611161
    Abstract: A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Min Oh
  • Patent number: 8610194
    Abstract: A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seiichi Aritome
  • Patent number: 8609543
    Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first and a second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer to have different thicknesses over the first and the second regions, forming a hard mask pattern by etching the hard mask layer, and etching the etch target layer using the hard mask pattern as an etch mask to form a target pattern having different densities over the first and the second regions.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myung-Ok Kim, Tae-Woo Jung
  • Patent number: 8605537
    Abstract: The column address circuit of a semiconductor memory device according to an aspect of the present disclosure includes a column address generation circuit configured to generate an internal dummy clock in response to a data output enable signal, generate an internal clock in response to a read enable signal, generate first count addresses in response to the internal dummy clock, and generate normal count addresses in response to the internal clock after the generation of the first count addresses, where the read enable signal is activated later than the data output enable signal, and a column address output circuit configured to store the first count addresses and the normal addresses and to generate column addresses by synchronizing the first count addresses and the normal addresses with output clocks, respectively.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min Su Kim, Jin Su Park
  • Patent number: 8604585
    Abstract: A fuse of a semiconductor device includes a plurality of first conductive patterns, and a plurality of second conductive patterns filling spaces between the first conductive patterns and formed of a material which has a greater specific resistance than the first conductive patterns.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Buem-Suck Kim
  • Patent number: 8605496
    Abstract: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee Bok Kang, Suk Kyoung Hong
  • Patent number: 8604830
    Abstract: A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Kyu Choi
  • Patent number: 8604537
    Abstract: There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Kwon Hong
  • Patent number: 8605519
    Abstract: A pump circuit includes a plurality of clock control circuits configured to transfer a clock to respective output terminals in response to respective pump-off signals or block the clock from being transferred to the respective output terminals, a plurality of charge pumps configured to generate respective high voltages by performing respective pumping operations in response to respective clock signals of the output terminals, and a plurality of switching circuits configured to transfer the respective high voltages to a final output terminal in response to respective control signals.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Moon Soo Sung
  • Patent number: 8604561
    Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
  • Patent number: 8603919
    Abstract: A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Dae Han
  • Patent number: 8604556
    Abstract: A method for fabricating a semiconductor device includes forming a recess pattern by selectively etching a substrate; forming a gate dielectric layer filling the recess pattern on the substrate; forming a groove by selectively etching the gate dielectric layer; forming a polysilicon electrode filling the groove; forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and forming a gate pattern by etching the electrode metal layer and the gate dielectric layer. The recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon-Young Koh
  • Patent number: 8598711
    Abstract: The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chi Hwan Jang
  • Patent number: 8601330
    Abstract: A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woo-Sik Jeong, Kang-Chil Lee, Jeong-Ho Cho, Kyoung-Shub Lee, Il-Kwon Kang, Sungho Kang, Joo Hwan Lee
  • Patent number: 8596544
    Abstract: An RFID tag includes an RFID chip, at least one sensor chip stacked on the RFID chip and interfaced with the RFID chip through a bump interface, and a filter layer stacked on the sensor chip to filter a sensing source introduced into the sensor chip.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee-Bok Kang
  • Patent number: 8601327
    Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park