Abstract: A BGA semiconductor package including: a semiconductor chip on which a chip pad is formed; a flexible member formed on the semiconductor chip; a metal pattern formed on one surface of the flexible member; a connection member for electrically connecting the pad and the metal pattern; and an external terminal electrically connected to the metal pattern. A method for fabricating the BGA semiconductor package including the steps of: fabricating a flexible member; forming a metal pattern on one surface of the flexible member; forming a pad on one surface of the semiconductor chip; attaching the flexible member onto the semiconductor chip in a manner that the pad is exposed; electrically connecting the pad and the metal pattern; and attaching an external terminal onto a predetermined region of the metal pattern.

Abstract: A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the first semiconductor layer. The first insulation layer, the first semiconductor layer, and the second insulation layer are then patterned to create openings that expose the buried diffusion region. A third insulation layer is formed on respective side walls of the openings on the exposed portions of the first semiconductor layer, first insulation layer and second insulation layer that form the openings. A first epitaxial layer is formed on the semiconductor substrate exposed through the openings. A second epitaxial layer is then formed on the first epitaxial layer to be connected to the first semiconductor layer, thereby forming an active base region and a second conductive type collector region in the second epitaxial layer of the first and second openings.

Abstract: Apparatus and method including a starting file storing portion for matching a large amount of configuration data between an exchanger and an initialized TMN repeater, and a modified file storing portion for storing modified information of configuration data managed by the exchanger, and outputting stored modified information to the TMN repeater after initialization, and if an operator stores exchanger configuration data into the starting file storing portion and stores modified configuration data into the modified file storing portion when initialization, the TMN repeater reads exchanger configuration data stored in the starting file storing portion, and updates corresponding managed object with read date. Then, the TMN repeater reads modified configuration data stored in the modified file-storing portion, and updates corresponding managed object with read data.

Abstract: A base transceiver station of a digital mobile telecommunication system which is separated into a remote site part including a radio frequency unit and a hub site part including components other than the radio frequency unit and wherein the hub site part is miniaturized so that the entire base transceiver station can be readily installed under the optimum conditions to maximize the quality of speech. A remote site part control system can be modified in a software manner with no addition of separate hardware resources when the entire base transceiver station is increased in capacity.

Abstract: Disclosed are a capacitor for semiconductor devices capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. The capacitor for semiconductor memory devices according to the present invention includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline TaxOyNz layer, and the total of x, y, and z in the crystalline TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.

Abstract: A member for a semiconductor package and a semiconductor package using the member, and a method for fabricating the semiconductor package are provided to simply connect chip pads provided on a semiconductor chip to external terminals. With the member for the semiconductor package and the package using the member according to the present invention, the chip pads can simply be connected with the corresponding external terminals. In addition, since the electrical paths between the chip pads and the external leads are relatively shortened, thus the electric properties are improved. Further, since the external terminal balls can be arranged regardless of the location of the chip pads, the semiconductor package can be easily designed and the size of the package can approximate the chip size and the plurality of external balls can be provided. Also, since it is possible to perform the package process with either the wafer or the individual chip, an application range can be flexibly extended.

Abstract: The present invention provides compounds represented by formulas 1a and 1b, and photoresist polymers derived from the same. The present inventors have found that photoresist polymers derived from compounds of formulas 1a, 1b, or mixtures thereof, having an acid labile protecting group have excellent durability, etching resistance, reproducibility, adhesiveness and resolution, and as a result are suitable for lithography processes using deep ultraviolet light sources such as KrF, ArF, VUV, EUV, electron-beam, and X-ray, which can be applied to the formation of the ultrafine pattern of 4G and 16G DRAMs as well as the DRAM below 1G: where R1, R2 and R3 are those defined herein.

Abstract: A method for reducing surface defects of a semiconductor substrate comprising selectively etching an insulation film formed on a semiconductor substrate and forming a contact hole, forming a conductive layer in a contact hole and on the upper surface of the insulation film, performing a Chemical Mechanical Polishing process on the conductive layer to expose the upper surface of the insulation film and forming a conductive layer plug in the contact hole, forming an oxide film on the upper surface of the conductive plug, and washing the conductive layer plug and the surface of the insulation film. In order to reduce surface defects of a semiconductor substrate, an oxide film is formed on the surface of the semiconductor substrate during the Chemical Mechanical Polishing process or after the Chemical Mechanical Polishing process, so that the efficiency of the post-washing process is heightened and the surface defects of the substrate is reduced.

Abstract: Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the first insulating film, a first, and a second impurity regions formed in the semiconductor substrate on both sides of the conductive layer patterns, a second insulating film formed on the first insulating film inclusive of the conductive layer patterns, a contact hole formed in the second insulating film on the conductive layer patterns, a plug formed in each of the contact holes, and wordlines formed the second insulating film inclusive of the plugs.

Abstract: The method of forming a plug of a semiconductor device includes sequentially forming a conductive film and an insulation film over a semiconductor substrate having a high density region and a low density region. The high density region has a greater number of structures formed thereover than the low density region. Next, a first CMP (chemical mechanical polishing) process, in which slurry for removing insulating film is used, is performed to selectively remove the insulating film and expose a top surface of the conductive film. Then a second CMP process, in which slurry for removing conductive film is used, is performed to selectively remove the conductive film and the insulating film and expose structures in the high density region.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract: Disclosed is an organic anti-reflective film composition suitable for use in submicrolithography, comprising a compound of Formula 13 and a compound of Formula 14 . The organic anti-reflective film effectively absorbs the light penetrating through the photoresist film coated on top of the anti-reflective film, thereby greatly reducing the standing wave effect. Use of organic anti-reflective films of the present invention allows patterns to be formed in a well-defined, ultrafine configuration, providing a great contribution to the high integration of semiconductor devices.

Abstract: A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference, a first bit inverter, an adder, a leading-zero anticipation circuit for anticipating the consecutiveness of leading zeros from the significands, a leading-zero counter for counting the anticipated number of leading zeros, a left shifter for shifting an output value from the adder, a second bit inverter for taking two's complement of an output value from the left shifter, an incrementer for incrementing an output value from the second bit inverter by one, a compensation shifter for shifting an output value from the incrementer, an exponent subtracter for subtracting the number counted by the leading-zero counter from the larger exponent, and a decrementer for decrementing an output exponent from the exponent subtracter by one.

Abstract: Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

Abstract: The present invention relates to photoresist monomers, polymers formed therefrom and photoresist compositions suitable for photolithography processes employing a DUV light source, such as KrF(249 nm) and ArF(193 nm); EUV; VUV; E-beam; ion-beam; and X-ray. Photoresist monomers of the present invention are represented by the following Chemical Formula 1: wherein, m is 1 or 2. Polymers of the present invention comprise repeating units derived from the comonomer of Chemical Formula 1, preferably together with monomers of the following Chemical Formula 2: wherein, R* is an acid-labile group, and W is 1 or 2.

Abstract: A photomask including chromium patterns divided into two groups in such a fashion that the chromium patterns in one of the two chromium pattern groups alternate, one by one, with the chromium patterns in the other chromium pattern group, the chromium patterns being formed on two quartz substrate for the two chromium pattern groups, respectively, to prepare for the photomask, two separate photomasks each having an increased space defined between adjacent chromium patterns thereof so as to avoid a severe diffraction of light passing between the adjacent chromium patterns. A method for forming micro patterns of a semiconductor device using the photomask is also disclosed.

Abstract: A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.

Abstract: The present invention discloses a method for forming a device trench isolation film for a semiconductor device having impurity regions at the sidewalls of the trench. The impurity regions increase the threshold voltage of the transistor and suppress an inverse narrow width effects. In addition, the method prevents or suppresses the phenomenon wherein an impurity in a channel region moves to the trench and lowers the threshold voltage of the transistor, decreases the leakage current, and overcomes a hump phenomenon by turning on a parasitic transistor at the sidewalls with the transistor in the active region. As a result, the electrical properties and reliability of the resulting semiconductor device are improved.

Abstract: A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

Abstract: A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper -electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.