Abstract: A stacked semiconductor package is formed by forming a semiconductor wafer having a plurality of semiconductor chips with chip pads on their upper sides, where the chips are arranged in pairs; sawing the wafer along edges of the semiconductor chips; adhering a bonding tape to adjacent pairs of the semiconductor chips, wherein conductive interconnections on the bonding tape electrically couple corresponding chip pads of adjacent chips; cutting the bonding tape so that only adjacent pairs of the chips remain attached to one another; and stacking the adjacent pairs of semiconductor chips so that the upper sides of the chips are substantially parallel. The method may include an additional step of adhering a plurality of solder balls on the bonding tape to serve as external leads of the package. Further, the adjacent pairs of semiconductor chips may be attached to opposite sides of a heat conducting plate which serves to dissipate heat generated by the chips.

Abstract: There is provided a method for fabricating a CMOS image sensor having enhanced reliability and light sensitivity, which comprises the steps of providing a substrate including photosensitive elements and metal wire; forming a first protecting film for protecting the elements over the substrate, covering the metal wire; forming a flattened spin-on-glass film on the first protecting film; forming a second protecting film for protecting the elements on the spin-on-glass film; forming color filter patterns on the second protecting film; forming a photoresist film for flattening on the color filter patterns and the second protecting film; and forming microlenses on the photoresist film. By using the flattened SOG film and a photoresist for flattening and pad opening, the present invention can accomplish the thickness uniformity of the color filter corresponding to each unit pixel, the wire-bonding pad devoid of the residuals of the color filter materials and the figure uniformity of the microlenses.

Abstract: Nonvolatile ferroelectric memory and method for fabricating the same can reduce fatigue caused by repetitive switching, drop an operation voltage, and increase an operation speed of the nonvolatile ferroelectric memory. The nonvolatile ferroelectric memory includes a plurality of wordlines formed in one direction, and a plurality of a control line and a sensing line pairs formed in a direction crossing the wordlines at fixed intervals. Unit cells of the memory formed at intersections of the wordlines and the control and signal line pairs each have first transistors formed between the control line and the sensing line with a drain coupled to a prescribed voltage. Second transistors in the unit cells have a drain coupled to the sensing line, a source coupled to a source of the first transistor, and a gate coupled to the wordline, and third transistors in the unit cells have a drain coupled to the control line, a source coupled to a gate of the first transistor, and a gate coupled to the wordline.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.

Abstract: A charge coupled device includes a plurality of photoelectric conversion regions; a plurality of vertical charge coupled devices (VCCDs) provided between the photoelectric conversion regions for transmission of charges generated at the photoelectric conversion regions in a first direction; and a horizontal charge coupled device (HCCD) coupled to the VCCDs and having a channel region including a plurality of channels for transmission of the charges previously transmitted through the VCCDs in a second direction. The channel region is formed such that one of the plurality of channels has a higher potential than the remaining channels. The remaining channels have potentials that gradually become lower than the highest potential moving in a direction away from the channel with the highest potential. The channel region transmits the charges within the HCCD so that the charges are gathered together centered around the channel having the highest potential during transmission of the charges.

Abstract: A method for controlling an automatic guide vehicle (AGV) in a semiconductor factory automation (FA) system, includes the steps of: a) receiving operating mode information of a process equipment changed by an operator; b) storing the operating mode information of the process equipment changed in a real-time database; c) carrying out a predetermined semiconductor process at an operating mode having a full automation mode and sending a process completion signal after the predetermined semiconductor process has been completed, wherein the predetermined semiconductor process is applied to a lot of semiconductor wafers; d) creating a queue in response to the process completion signal; e) checking the operating mode information of the process equipment stored in the real-time database in response to the queue; f) inactivating the AGV by interrupting a transmission of the queue to the AGV if the operating mode information of the process equipment stored in the real-time database is not the full automation mode; and

Abstract: A method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, includes the steps of receiving the external signal to generate a full-swing level signal, dividing the full-swing level signal into a first signal and a second signal in synchronization with the data strobe signal, wherein the first signal is activated in synchronization with rising edges of the data strobe signal and the second signal is activated in synchronization with falling edges of the data strobe signal, aligning the first signal and the second signal with one of both edges of the data strobe signal, and aligning the aligned first and second signals with one of both edges of a main clock.

Abstract: A base transceiver station of a digital mobile telecommunication system comprising a master base transceiver station device (master BTS device) and a plurality of remote radio frequency units separated from the master BTS device and installed at a remote site therefrom for processing radio frequency signals. The master BTS device and the radio frequency units are interconnected via a remote interfacing unit. Therefore, the base transceiver station can become so much smaller in size and lighter in weight that it can be readily installed in a place effecting the optimum propagation. Furthermore, the remote interfacing unit can remotely control and monitor the status of the remote radio frequency units via a radio frequency cable without using a separate control cable.

Abstract: A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depositing a metal layer by CECVD method so that the metal layer is selectively deposited at the portion in which the chemical enhancer is formed, removing the photosensitive film and chemical enhancer, and forming a diffusion barrier layer spacer at the sidewall of the metal layer to form an upper metal wiring. Therefore, the disclosed method can solve poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a high integration semiconductor device.

Abstract: A silicon-on-insulator (SOI) device has a reversed stacked capacitor cell and body contact structure. The SOI device includes a semiconductor layer, an isolation film, a first gate, a first source region, a first drain region, a second gate, a second source region, a second drain region, a capacitor, and first, second and third impurity regions. The semiconductor layer includes a gate surface and another surface. The isolation film is of a trench tpye formed in the gate surface of the semiconductor layer. It has a lower surface at a level between the gate surface and the another surface. The isolation film also defines a first device formation region and a second device formation region. The first gate, first source region and first drain region are formed in the first device formation region. The second gate, second source region and second drain region are formed in the second device formation region.

Abstract: The method of the present invention includes providing a silicon substrate having an impurity region, forming an inter-layer insulating film having a contact hole in the impurity region and forming a titanium film and titanium nitride film in the contact hole. The method of the present invention further includes conducting a heat treatment to cause a reaction between the titanium film and the silicon substrate and forming a tungsten plug on the titanium nitride film in the contact hole. The device of the present invention including the bit lines are made up of a first inter-layer insulating film on the substrate having a first contact hole over the impurity region, a titanium film in the first contact hole, a titanium nitride film on the titanium film, a titanium silicide film on the silicon substrate wherein the titanium silicide film does not include an agglomerate, a tungsten plug on the titanium nitride film in the first contact hole and a circuit element on the first inter-layer insulating film.

Abstract: The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

Abstract: ESD protection circuit which can minimize fluctuation of a gate voltage with an ESD input voltage, for improving an ESD protection capability, including a first transistor connected to an input pad for discharging an ESD charge, a capacitor and a diode connected to the input pad for applying a gate voltage to a gate of the first transistor to improve a bipolar driving capability of the first transistor, a second transistor for controlling drive of the first transistor when the chip is operative, and a resistor for delaying transmission of an ESD charge to an inner circuit when the ESD charge is received at the input pad.

Abstract: An improved semiconductor device, and a corresponding fabrication method thereof, are provided that include a ground region defined in a semiconductor substrate. A hole is formed using a known electropolishing system to electropolish a portion of a bottom surface of the substrate which corresponds to the ground region. A metal layer is formed on the bottom surface of the substrate and in the hole. The metal layer serves as ground by being linked with a ground metal line formed on a substrate surface.

Abstract: The present invention relates to a copolymer resin for a photoresist used in far ultraviolet ray such as KrF or ArF, process for preparation thereof, and photoresist comprising the same resin. The copolymer resin according to the present invention is easily prepared by conventional radical polymerization due to the introduction of mono-methyl cis-5-norbonen-endo-2,3-dicarboxylate unit to a structure of norbornene-maleic anhydride copolymer for photoresist. The resin has high transparency at 193 nm wavelength, provides increased etching resistance and settles the problem of offensive odor occurred in the course of copolymer resin synthesis. Further, as the resin composition can be easily controlled due to the molecular structure, the resin can be manufactured in a large scale.

Abstract: Provided are methods for forming ferroelectric capacitors, which prevent decreasing ferroelectric characteristics due to the reaction of a ferroelectric layer with hydroxyl group induced from a inter-layer insulating film which will be formed and contacted with the ferroelectric layer after the formation of the ferroelectric capacitor. After a ferroelectric film such as Pb(Zr,Ti)O3 (PZT) is formed, a ZrO2 film, which is insulator and excellent in diffusion barrier characteristics, is formed so as to enclose the entire ferroelectric layer in order to prevent the damage generated by the reaction. The characteristics of the ferroelectric capacitor are enhanced by the invention.

Abstract: A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the trench, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.

Abstract: The present invention provides compounds represented by formulas 1a and 1b; and photoresist polymers derived from the same.

Abstract: A method is disclosed for forming fine photoresist patterns on semiconductor devices using a modified, two-step dry develop process using a fluorine-containing gas to produce hydrophobic SiOx passivation layers on the sidewalls of the photoresist patterns. These passivation layers increase the structural stability of the fine photoresist patterns and prevent moisture within an air from cohering on the photoresist patterns when the semiconductor substrate is subsequently exposed to the air. Accordingly, the present invention improves the processing margins for very high aspect ratio photoresist patterns resulting in reduced rework and increased yield on very highly integrated semiconductor devices.

Abstract: A method for fabricating a conductive line pattern for a semiconductor device including the steps of: forming a gate insulation film on the upper surface of a semiconductor substrate; forming a polysilicon layer on the upper surface of the gate insulation film; forming a WNx film on the upper surface of the polysilicon layer; forming a first insulation film on the upper surface of the WNx film; patterning the first insulation film, the WNx film and the polysilicon layer, to form a conductive line pattern; and selectively oxidizing the polysilicon layer. With the method, in view of forming the conductive line pattern in the WNx/poly-Si structure, the thermal treatment processes are reduced in number, so that the thermal stress applied to the conductive line pattern is diminished, and thus, a reliability of the semiconductor device is improved.