Patents Assigned to Hyundai Electronics Industries Co., Ltd.
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Patent number: 6642095Abstract: The present invention relates to semiconductor device and a fabricating methods thereof which enable to improve device characteristics such as threshold voltage and the like by preventing p type impurities doping a gate from penetrating into a channel region of a substrate through a SiO2 layer. The present invention also relates to preventing transconductance due to reciprocal reaction of traps from decreasing by re-oxidation, wherein a first and a second oxynitride layer are formed at a first interface between a SiO2 layer and a gate of p-doped polysilicon and a second interface between the SiO2 layer and a silicon substrate, respectively.Type: GrantFiled: May 1, 2001Date of Patent: November 4, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Seok-Woo Lee
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Patent number: 6642100Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.Type: GrantFiled: June 28, 2001Date of Patent: November 4, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Bee-Lyong Yang, Seaung-Suk Lee, Suk-Kyoung Hong, Nam-Soo Kang
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Publication number: 20030203540Abstract: A stacked semiconductor package including: a first chip; a plurality of first leads of which one side of each of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including holes for exposing a predetermined portion of each of the plurality of the first leads, and the first molding compound does not cover a side of the first leads opposite the holes; a first conductive portion formed within the holes included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically coType: ApplicationFiled: May 29, 2003Publication date: October 30, 2003Applicant: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD.Inventor: Ki-Rok Hur
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Patent number: 6638817Abstract: The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other are defined; a plurality of transistors each having a gate electrode formed by interleaving a gate insulating film on the active regions and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions, and having a lower electrode and a upper electrode formed by interleaving a capacitor insulating film on the lower electrode; a plurality of bit lines connected to one of the source and drain regions of the plurality of transistors; and a plurality of word lines comprised of first word lines and second word lines arranged in parallel which are vertical to the direction in which the bit lines are arranged, and selectively connect the gate electrodes oType: GrantFiled: December 20, 2001Date of Patent: October 28, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Kwan Kim
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Publication number: 20030197203Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.Type: ApplicationFiled: April 14, 2003Publication date: October 23, 2003Applicant: Hyundai Electronics Industries Co., Ltd.Inventors: Sang Bae Yi, Jae Seung Choi
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Publication number: 20030197268Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.Type: ApplicationFiled: May 22, 2003Publication date: October 23, 2003Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Il-Suk Han
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Patent number: 6636570Abstract: A phase detection apparatus for receiving an I-channel signal an a Q-channel signal as a received signal modulated with a quadrature phase-shift keying and compensating a phase rotation error of the received signal, includes: a phase detector for detecting a phase error through the use of the I- and Q-channel signals and providing an error signal; a shifting unit for shifting said I-channel signal by a plurality of predetermined different numbers of bits and providing shifted I-channel signals; a first multiplexing unit, in response to an external selection signal, for selecting signals among said shifted I-channel signals; a subtracting unit for providing difference signals between said selected signals and said Q-channel signal; a comparison unit for comparing said difference signals with a reference signal and producing logic signals; a logic gate for producing a logically ORed signal of said produced logic signals; and a second multiplexing unit, in response to said ORed signal, for selecting a signal froType: GrantFiled: June 21, 2000Date of Patent: October 21, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Han-Jun Choi, Suk-Jun Lee
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Patent number: 6635927Abstract: The present invention relates to the field of the semiconductor fabrication. Also, the objects of the present invention are to provide a semiconductor device and method for fabricating the same having the MOS transistors capable of improving the thermal conduction characteristics and the punch-through and the DIBL effect. To accomplish these objects, the present invention provides the semiconductor device including a semiconductor substrate; a first insulating layer, a selected material layer and a second insulating layer orderly stacked on said semiconductor substrate; and a semiconductor layer formed on the second insulating layer for providing an active area where MOS transistors are formed, wherein, said material layer provides a path for emitting heat generated from said MOS transistors.Type: GrantFiled: March 11, 2002Date of Patent: October 21, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jin Hyeok Choi
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Patent number: 6632903Abstract: The present invention relates to a semiconductor device using a copolymer-containing photoresist, and a process for manufacturing the same. As a norbornene derivative (monomer) having a hydrophilic group is synthesized and introduced to the backbone chain of a polymer, the polymer according to the present invention has excellent etching resistance and heat resistance, which are the characteristic points of alicyclic olefin structure, and provide excellent resolution due to prominent enhancement of adhesiveness resulted from introducing a hydrophilic group (—OH).Type: GrantFiled: August 21, 2001Date of Patent: October 14, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Min Ho Jung, Jae Chang Jung, Cheol Kyu Bok, Ki Ho Baik
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Patent number: 6633062Abstract: A semiconductor device for use in a memory cell includes an active matrix an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of lower electrodes formed on top of the conductive plugs, Ta2O5 films formed on the lower electrodes, composite films formed on the Ta2O5 films and upper electrodes formed on the composite films.Type: GrantFiled: October 15, 2002Date of Patent: October 14, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Kim Min-Soo, Lim Chan
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Patent number: 6632702Abstract: A method for fabricating a color image sensor for scanning and converting an optical image into electrical signals, includes the steps of: (a) forming a P-type semiconductor layer on a substrate; (b) forming field oxide layers on the P-type semiconductor layer to define regions for red, green and blue photodiodes; (c) providing an ion implantation mask having different mask patterns for the red, the green and the blue photodiodes; (d) implanting impurity ions into the P-type semiconductor layer through the use of said ion implantation mask to form N-type diffusion regions in the P-type semiconductor layer; and (e) applying a thermal process to the resulting structure to form different first, second and third depletion regions corresponding to the red, the green and the blue photodiodes.Type: GrantFiled: March 7, 2002Date of Patent: October 14, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jae-Won Eom, Do-Young Lee, Kang-Jin Lee, Chan-Ki Kim, Ki-Nam Park
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Patent number: 6633335Abstract: The present invention relates to a picture display using CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a CMOS image sensor having a testing circuit embedded therein and a method for verifying operation of the CMOS image sensor using the testing circuit. The CMOS image sensor according to the present invention includes a control/interface unit for controlling its operation sensor using a state machine and for interfacing the CMOS image sensor with an external system; a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light; a converter for converting the analogue signals into digital signals to be processed in a digital logic circuit; and a testing circuit for verifying operations of the converter and the control/interface unit, by controlling the converter.Type: GrantFiled: February 26, 1999Date of Patent: October 14, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Oh Bong Kwon, Woodward Yang, Suk Joong Lee, Gyu Tae Hwang
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Publication number: 20030191259Abstract: The present invention relates to photoresist monomers, polymers formed therefrom and photoresist compositions suitable for photolithography processes employing a DUV light source, such as KrF (249 nm) and ArF(193 nm); EUV; VUV; E-beam; ion-beam; and X-ray.Type: ApplicationFiled: March 21, 2003Publication date: October 9, 2003Applicant: Hyundai Electronics Industries Co., Ltd.Inventors: Chi Hyeong Roh, Jae Chang Jung
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Patent number: 6630709Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.Type: GrantFiled: December 19, 2000Date of Patent: October 7, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang-Hoan Chang, Ki-Seog Kim, Keun-Woo Lee, Sung-Kee Park
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Patent number: 6631059Abstract: ESD protection circuit which can effectively protect a product with three or two leveled electrodes in any cases when an external (+) or (−) ESD charge flows into the product, including, in case of the ESD protection circuit for a product with three leveled electrodes(VP, VDD and GND), a first conduction type bipolar transistor and a second conduction type bipolar transistor connected in parallel between an input terminal and a GND, wherein the first conduction type bipolar transistor has a base terminal with a VP voltage applied thereto and the second conduction type bipolar transistor having a base terminal with a VDD voltage applied thereto, and collectors and emitters thereof connected to the input terminal or the GND.Type: GrantFiled: August 18, 2000Date of Patent: October 7, 2003Assignee: Hyundai Electronics Industries Co. Ltd.Inventor: Kyoung Kuk Kwon
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Patent number: 6627533Abstract: A method of manufacturing an insulating film in a semiconductor device is disclosed. The method comprises the steps of forming a SOD film on the entire structure to fill any distance between conductive layer patterns and after performing a curing process, forming a hard mask film on the SOD film, wherein the silicon oxide film is deposited by plasma deposition method using SiH4 and N2O as a reaction gas at a low-temperature and at a low-pressure and wherein in a stabilization step, the supply amount of SiH4 is greater than that of N2O and in a deposition step, the supply amount of N2O is greater than that of SiH4.Type: GrantFiled: June 13, 2001Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang Tae Ahn, Jung Gyu Song
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Patent number: 6627384Abstract: The present invention relates to photoresist compositions for resist flow process and processes for forming a contact hole pattern using the same. In particular, the present invention relates to photoresist composition comprising a thermal curing agent which cures photoresist composition at an elevated temperature. In one embodiment, the thermal curing agent comprises a thermal acid generator and a curing compound. Preferably, the curing compound comprises a cross-linking moiety which is capable of curing the photoresist composition when reacted with the acid that is generated by the thermal acid generator. Photoresist compositions of the present invention reduces or eliminate overflow of photoresist during a resist flow process, thereby preventing a contact hole pattern from being destroyed. In addition, photoresist compositions of the present invention allow formation of uniform sized patterns and increase in etching selection rate.Type: GrantFiled: October 27, 2000Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyeong Soo Kim, Jae Chang Jung
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Patent number: 6627462Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a silicon substrate, a transistor formed on the silicon substrate, a capacitor structure formed over the transistor, a metal interconnection for electrically connecting the capacitor structure to the transistor, a barrier layer formed on top of the metal interconnection and an inter-metal dielectric (IMD) layer formed on top of the barrier layer, wherein the barrier layer is made of a material such as A12O3 or the like. The IMD layer is formed by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.Type: GrantFiled: June 28, 2000Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Woo-Seok Yang, Seung-Jin Yeom, Yong-Sik Yu
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Patent number: 6627378Abstract: The present invention provides photoresist compositions for a Top-surface Imaging Process by Silylation (TIPS) and processes for using the same. The photoresist composition comprising a photoresist resin, a photoacid generator, an organic compound, and an amphoteric compound. The amphoteric compound prevents or reduces the amount of acid diffusion into the unexposed area and improves the contrast between the exposed and the unexposed areas. This reduction or prevention of acid diffusion into the unexposed areas reduces line edge roughness (LER).Type: GrantFiled: November 10, 2000Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., LtdInventor: Cha Won Koh
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Patent number: 6628134Abstract: A DC stress supply circuit for a semiconductor circuit having a plurality of DC stress supply terminals and a plurality of switches in which the DC stress terminals are connected to some nodes of the unit elements included in the semiconductor circuit, respectively. The switches allow a DC stress to be applied selectively, to the nodes from the DC stress terminals according to a control signal.Type: GrantFiled: June 29, 2000Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Chang Yeol Lee