Abstract: In a mobile communication system of multi-cell environment, a pico-cell indicator is installed at predetermined positions for easy cell-registration change of a mobile station from a micro-cell service area to a pico-cell service area.

Abstract: A device isolation structure and method for a semiconductor device according to the present invention includes forming first and second trenches by etching predetermined regions of a semiconductor substrate, forming a buried insulating film in the trenches, filling in the trenches by depositing single crystal silicon film on the buried insulating film by a silicon epitaxy method, and forming a field insulating film on portions of the semiconductor substrate between the first and second trenches. The field oxide film isolating the single crystal silicon layers fills the adjacent trenches, thus isolating semiconductor devices, such as a high voltage device and a low voltage device, to be fabricated in the single crystal silicon layers.

Abstract: The black level calibration apparatus includes a black level clamp circuit which generates a black level clamp signal based on a calibrated reference voltage. A correlated double sampling/automatic gain control (CDS/AGS) circuit performs sample/hold and automatic gain control operations on an analog image signal based on the black level clamping signals. An analog-to-digital converter converts the analog image output from the CDS/AGS circuit into a digital image signal. A control signal setting circuit compares the black level value of the digital image signal with a black level calibration value, and sets a digital control signal based on the comparison. A reference voltage calibration circuit generates the calibrated reference voltage in accordance with the digital control signal.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: The present invention provides an organic anti-reflective film composition suitable for use in submicrolithography. The composition comprises a compound of chemical formula 11 and a compound of chemical formula 12. The organic anti-reflective film effectively absorbs the light penetrating through the photoresist film coated on top of the anti-reflective film, thereby greatly reducing the standing wave effect. Use of organic anti-reflective films of the present invention allows patterns to be formed in a well-defined, ultrafine configuration, providing a great contribution to the high integration of semiconductor devices. wherein a, b, c, R′, R″, R1, R2, R3, and R4 are those defined herein.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: A method for manufacturing an aluminum oxide film for use in a semiconductor device which includes the following steps: preparing a semiconductor substrate and setting the semiconductor substrate in a reaction chamber; supplying modified trimethyl aluminum (MTMA) as an aluminum source material into the reaction chamber so that it could be absorbed on the semiconductor substrate; discharging unreacted MTMA or by-product through a first pump by permitting nitrogen gas to flow into the reaction chamber and purging the chamber for vacuum status; supplying an oxygen source into the reaction chamber so that it could be absorbed on the semiconductor substrate; and discharging an unreacted oxygen source or by-product through a second pump by permitting nitrogen gas to flow into the reaction chamber and purging the chamber for vacuum status.

Abstract: Fabricating thin film transistors. A gate electrode is formed on a substrate. A gate oxide film is then formed on the gate electrode. A polysilicon layer is deposited on the gate oxide film. An impurity ion is implanted into the polysilicon layer to control a threshold voltage of the polysilicon layer. A mask is formed on the polysilicon layer above the gate electrode, having the same width as the gate electrode. A second impurity ion is implanted into the exposed portion of the polysilicon layer using the mask, to form a lightly doped offset region on a drain region. The mask is removed. A second mask is formed on the polysilicon layer so as to cover a portion of the gate electrode and the light doped offset region. A Third impurity ion is implanted into the polysilicon layer using the second mask to form source/drain regions. The mask is removed.

Abstract: Disclosed are a chip size stack package and a method of fabricating the same. Two semiconductor chips are arranged such that their bond pads-forming surfaces are opposed to each other. Insulating layers are applied to the bond pads-forming surfaces of the semiconductor chips, and via-holes for exposing bond pads are formed in the insulating layers. Metal traces which are exposed at both sides of the insulating layers are formed on the via-holes, whereby the insulating layers are bonded to each other and the metal traces are also bonded to each other. One ends of metal wires are connected to the metal traces which are exposed at the insulating layers, and both sides of the semiconductor chips are molded by an encapsulate such that the other ends of the metal wires are exposed. Instead of the metal wires, pattern tapes can be used. One ends of the pattern tapes are electrically connected to the metal traces when the insulating layers are bonded to each other, and the other ends of the pattern tapes are exposed.

Abstract: The present invention provides photoresist monomers, photoresist polymers derived from the same, processes for producing such photoresist polymers, photoresist compositions comprising such polymers, and processes for producing a photoresist pattern using such photoresist compositions. In particular, photoresist monomers of the present invention comprise a moiety of Formula 4: where R1, R2, R3 and R4 are those defined herein. Photoresist polymers of the present invention have a relatively high etching resistance, and therefore are useful in a thin resist process and a bilayer photoresist process. Moreover, photoresist polymers of the present invention have a high contrast ratio between an exposed region and a non-exposed region.

Abstract: The present invention discloses a photoresist polymer of following formula 1, and a photoresist composition comprising the same: where AC1, AC2, x and y are those defined herein. The photoresist composition has excellent transparency in deep ultraviolet region, etching resistance and heat resistance, and can form a good pattern without a developing step. Accordingly, the photoresist composition can be applied to a high density minute pattern below 0.15 &mgr;m (e.g., for fabrication of DRAM over 1G), and efficiently employed for the lithography process using ArF, KrF, VUV, EUV, E-beam and X-ray.

Abstract: The present invention relates to novel monomers which can be used to form polymers which are useful in a photolithography employing a light source in the far ultraviolet region of the light spectrum, copolymers thereof, and photoresist compositions prepared therefrom. Photoresist monomers of the present invention are represented by the following Chemical Formula 1: wherein, R is substituted or non-substituted linear or branched (C1-C10) alkyl, substituted or non-substituted (C1-C10) ether, substituted or non-substituted (C1-C10) ester, or substituted or non-substituted (C1-C10) ketone; X and Y are independently CH2, CH2CH2, oxygen or sulfur; and i is 0 or an integer of 1 to 2.

Abstract: In an apparatus for gamma correcting image data including a first image data, a second image data and a third image data, the apparatus includes: a first clock generator for generating a first clock; a second clock generator for generating a second clock, wherein the second clock has a frequency a predetermined times as fast as the first clock; an image data input unit for storing the image data in response to a first clock; a first selecting unit for selectively outputting the image data in response to a second clock; a second selecting unit for selectively outputting a starting point value of corresponding image data in response to the second clock; a third selecting unit for selectively outputting a gamma slope value of corresponding image data in response to the second clock; a piecewise gamma correction unit for receiving output values from the first, the second and the third selecting unit to generate gamma corrected image data; and an output unit for storing the gamma corrected image data a predetermin

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

Abstract: The present invention provides a polymer that can be used as an anti-refelctive coating (ARC) polymer, an ARC composition comprising the same, methods for producing the same, and methods for using the same. The polymer of the present invention is particularly useful in a submicrolithographic process, for example, using KrF (248 nm) or ArF (193 nm) lasers as a light source. The polymer of the present invention comprises a chromophore that is capable of absorbing light at the wavelengths used in a submicrolithographic process. Thus, the ARC of the present invention significantly reduces or prevents back reflection of light and the problem of the CD alteration caused by the diffracted and/or reflected light. The ARC of the present invention also significantly reduces or eliminates the standing wave effect and reflective notching.

Abstract: There is disclosed a code addressable memory (“CAM”) cell in a flash memory device. In order to stabilize the operation of the CAM cell in a flash memory device operating at a low voltage, the present invention manufactures a CAM cell in which a floating gate is formed to extend on more than two active regions and more than two cell arrays are connected in parallel commonly using a source region and a drain region. Therefore, the present invention can increase the gate-coupling ration of the CAM cell, thus stabilizing the operation of the CAM cell at a device for low-voltage use.

Abstract: A method of allocating frame offset and link in a base station in which performance of digital telecommunications system is enhanced by allocating a resource in such a manner that loads of the link and frame offset are dispersed when communication channels for use of handoff are allocated, and soft handoff can be occurred when the frame offset is allocated, has an advantage in that the link and frame offset are dynamically allocated when requesting handoff so that loads can be evenly distributed between the link and the frame offset. Thus, data loss between the communication channel and the control station may be minimized, and the mobile station may timely perform handoff, thus enabling a stable call handling service.

Abstract: An interrupt controller can execute a faster interrupt service routine after an occurrence of the interrupt by writing branch instructions upon initialization of the computer environment in advance of the actual interrupt. The interrupt controller includes an interrupt mask register that receives, and stores an interrupt on/off instruction from a CPU. An interrupt priority register receives and stores an interrupt priority instruction from the CPU. An interrupt mask circuit unit selectively receives and forwards an interrupt generating signal from peripheral devices in response to an interrupt on/off instruction from the interrupt mask register. A priority determining circuit unit receives the interrupt generating signals from the interrupt mask circuit unit, determines priorities of the interrupt signals in response to the interrupt priority instruction from the interrupt priority register, and forwards an interrupt priority signal to an interrupt terminal of the CPU.

Abstract: A capacitor having a storage electrode and a plate electrode, wherein both are made of metal or metal oxide, a high dielectric film formed between the electrodes, and a method of manufacturing the same. A diffusion prevention film is found at the side of the storage electrode and on the plate electrode. Therefore, the invention prevents deterioration of the property in the dielectric film due to penetration of hydrogen ions during a subsequent thermal process thereby improving the reliability of a device.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.