Patents Assigned to IBM
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Patent number: 4280197Abstract: A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal.Type: GrantFiled: December 7, 1979Date of Patent: July 21, 1981Assignee: IBM CorporationInventor: Eugene S. Schlig
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Patent number: 4275968Abstract: Printer having a sheet feed and drum transport assembly and an array transport assembly, these assemblies having critical operating parameters whose profile is measured during a nonprinting cycle executed for that purpose. These critical operating parameter values are sorted and used as the values of the respective critical parameters during the printing cycles after the profiling cycle. The values may be updated according to detected variances occurring during the printing cycles. In addition, the value of the paper position is determined during an initial printing cycle and stored and used in subsequent cycles.Type: GrantFiled: April 30, 1979Date of Patent: June 30, 1981Assignee: IBM CorporationInventor: John W. Irwin
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Patent number: 4267465Abstract: A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.Type: GrantFiled: January 15, 1979Date of Patent: May 12, 1981Assignee: IBM CorporationInventors: Werner Haug, Joerg Gschwendtner, Robert Schnadt
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Patent number: 4267407Abstract: For the multiplex transmission of coded speech signals in periodic frames, single segments (blocks of coded samples) are selectively suppressed for redundancy reduction, and are replaced on the receiver side by optimally correlated subsections of equal length from previously transmitted segments. On the transmitter side, a multiplicity of compare operations are made for each speech signal, between the respective newest coded segment and a step wise shifted subsection window of previous segments, to determine the best correlated subsection, i.e. the one which is most suitable as replacement and the respective relative offset and correlation. From a group of speech signals, the one signal, or several signals, having the best correlation is selected for suppression of a segment before transmission. Instead of each missing segment an indication of the corresponding optimum offset is transmitted in the frame header.Type: GrantFiled: September 27, 1979Date of Patent: May 12, 1981Assignee: IBM CorporationInventors: Hans R. Schindler, Peter Vettiger
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Patent number: 4264832Abstract: This is a feedback amplifier incorporating shunt feedback pairs which are emitter coupled for differential input transimpedance configuration whose characteristic includes a low differential input impedance and a high common load impedance that uses low input offset voltages to initiate the amplification and a latch coupled thereto to latch and amplify the amplifier input causing the effective amplifier input to be several orders of magnitude greater than the initial offset voltages. Thus, the amplifier of the invention uses the latch to not only sense the output of the amplifier but also the drive and reinforce the amplifier input through feedback.Type: GrantFiled: April 12, 1979Date of Patent: April 28, 1981Assignee: IBM CorporationInventor: Anatol Furman
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Patent number: 4262331Abstract: A self-adaptive computer load control apparatus and method are disclosed for allocating servicing time by a Central Processing Unit (CPU) to several Peripheral Processing Units (PE) under processing overload conditions. Each PE contains registers for storing the value of an expected interval of time between consecutive service periods, for storing the time of commencement of the last service period, and for storing the time of commencement of the present service period. Each PE also includes a comparator for comparing the difference between the times of commencement of the last and present service periods with the value of the expected interval between consecutive service periods. A control word generator is included in each PE for specifying the number of processing steps to be performed by the CPU during the present service period for the respective PE's.Type: GrantFiled: October 30, 1978Date of Patent: April 14, 1981Assignee: IBM CorporationInventors: Joseph W. Freeland, John E. Gaffney, Jr., Irwin L. Isert
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Patent number: 4262356Abstract: A method and a system are disclosed for synchronizing within a recurrent time frame the starting points of the transmissions from the various stations in a TDMA network wherein N stations distributed among M separate zones covered by M different down-link frequencies exchange pulse bursts through a satellite, each pulse burst being comprised of a preamble, a unique word, the transmitting station's address, and traffic data. The satellite includes a global beam antenna which covers all of the M zones and is adapted to receive M different up-link frequencies, means for converting these M up-link frequencies to M corresponding down-link frequencies, and M directional beam antennas covering the M zones, each of said M antennas being adapted to transmit the down-link frequency associated with the particular zone it covers. The bursts transmitted by the various stations are assigned a predetermined position within the frame.Type: GrantFiled: September 13, 1979Date of Patent: April 14, 1981Assignee: IBM CorporationInventors: Alex Lautier, Jean L. Monrolin
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Patent number: 4262316Abstract: For producing a transducer access opening in a stack of rotating flexible magnetic record disks, a co-rotating part axially deflects the peripheral edges of selected disks for partially axially separating same. The co-rotating part may take the form of a thin disk, several thin disks, or shaped as a roll. The axis of the roll is obliquely inclined against the disk pack rotational axis. The roll has a resilient surface such that, after the roll has been inserted into the disk pack, the flexible disks move up the outer surface of the roll to be deflected.Type: GrantFiled: July 30, 1979Date of Patent: April 14, 1981Assignee: IBM CorporationInventors: Kurt Hartmann, Horst Matthaei
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Patent number: 4259366Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs and OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array.Type: GrantFiled: January 17, 1980Date of Patent: March 31, 1981Assignee: IBM CorporationInventors: P. S. Balasubramanian, Claude L. Bertin, Stephen B. Greenspan
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Patent number: 4253775Abstract: A doctor blade is used to apply a powdered toner to the depleted regions of a resistive thermal transfer ribbon. The ribbon is then moved adjacent a heating electrode that passes current through a resistive substrate of the ribbon so that a transverse line on the ribbon is heated and the added toner is fused in the depleted regions of the ribbon. The heated area of the ribbon is thereafter compressed by a cold roller to provide a uniform re-inked surface.Type: GrantFiled: June 29, 1979Date of Patent: March 3, 1981Assignee: IBM CorporationInventors: Walter Crooks, Keith S. Pennington
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Patent number: 4238842Abstract: A computer paging store memory utilizing line addressable random access memories (LARAM) including charge coupled device (CCD) shift registers in which data is read out of the memory for utilization in a block storage memory without loss of refresh time due to the refresh of individual CCD shift registers. The memory is organized as a number of parallel-connected memory storage units, each of which includes a separate interface logic, a refresh control and a number of memory array units, each of which in turn is constructed of LARAM devices, each of which must be refreshed within a predetermined time interval. Data is normally read out from the LARAM devices one at a time in sequence. During the readout operation, a detection is continuously made which determines whether the next LARAM device in sequence must be refreshed during the subsequent readout time period.Type: GrantFiled: December 26, 1978Date of Patent: December 9, 1980Assignee: IBM CorporationInventor: Frederick J. Aichelmann, Jr.
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Patent number: 4188649Abstract: An AC magnetic erase head having improved AC erase characteristics, the magnetic head being formed of two half core elements of a magnetic material, preferably ferrite, defining an irregular edged or jagged-edged gap, and including a non-magnetic substance, preferably glass, within the gap. The magnetic head is preferably produced by thermally etching ferrite magnetic material forming the half core elements by means of relatively prolonged heat soak at an elevated temperature.Type: GrantFiled: December 5, 1977Date of Patent: February 12, 1980Assignee: IBM CorporationInventors: Samuel D. Cheatham, Neil L. Robinson, Edmond W. Smathers
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Patent number: 4070501Abstract: A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically comprising raised metallic stripes, is formed atop the substrate. A first level dielectric material is then deposited in blanket fashion so that the topology of the insulator conforms to the topology of the pattern. Next, a material such as polymer is deposited which tends to form a planar surface, with a greater thickness of polymer accumulating between the protuberances of the insulator than atop said protuberances. A mask is then applied, exposed and developed at selected regions where via holes are to be formed in the dielectric. A small amount of the polymer is etched, preferably in a plasma, to expose the insulator. Then the latter is etched to form the via holes. Accurately located via holes are formed, even if the mask is misaligned.Type: GrantFiled: October 28, 1976Date of Patent: January 24, 1978Assignee: IBM CorporationInventors: Vivian Ruth Corbin, James Edward Hitchner, Bisweswar Patnaik, Chung-Yu Ting
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Patent number: 4069488Abstract: A system for controlling a plurality of machine tools in which the central processor communicates data transactions to and from a plurality of tool controllers, each of which is operatively associated with a machine tool. Each of the controllers comprises at least one machine tool control unit which is adapted to provide a digital output to the associated machine tool for controlling a particular tool function and/or for receiving from the machine tool a digital input indicative of a particular tool condition. The central processor has connected thereto a main multiple-channel data bus for conducting data transactions by transferring parallel bits of data to and from the processor. The system also includes a plurality of multiple-channel unit data buses, each of which is connected to one of the tool control units.Type: GrantFiled: April 2, 1976Date of Patent: January 17, 1978Assignee: IBM CorporationInventors: Robert M. Fiorenza, Alan J. Fleming, Ralph J. Gerlach, Larry W. Holmstrom, John C. Pace
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Patent number: 4062040Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.Type: GrantFiled: March 24, 1977Date of Patent: December 6, 1977Assignee: IBM CorporationInventors: Shakir Ahmed Abbas, Robert Charles Dockerty
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Patent number: 4060427Abstract: A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate.The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.Type: GrantFiled: April 5, 1976Date of Patent: November 29, 1977Assignee: IBM CorporationInventors: Conrad A. Barile, Robert M. Brill, John L. Forneris, Joseph Regh
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Patent number: 4058887Abstract: A method of manufacturing an insulated gate field effect transistor comprising providing a semiconductor body portion of one type conductivity, providing on a surface of said body portion an impurity masking layer having two adjacent apertures with the portion of the masking layer between said apertures and part of its thickness being of a masking material other than silicon dioxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of opposite type conductivity in said body portion, subjecting at least the surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon dioxide that penetrates into the body portion except where masked by the oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated from and over the surface portionType: GrantFiled: October 13, 1972Date of Patent: November 22, 1977Assignee: IBM CorporationInventor: David Dewitt
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Patent number: 4056846Abstract: In a data processing system having a plurality of channels that are organized for separately processing the operations of specific I/O devices and the operations that are background to these specific operations, apparatus for transferring the background processing from one channel to another channel to distribute the background processing load. A system of registers and lines connect these registers to the channels for controlling these operations. Each channel processor has a request register for use in designating that background processing has been completed and that processing of a device oriented portion of a channel program is to begin, and a completion register set by an associated I/O processor for use in signifying that processing of a device oriented portion of a channel program has been completed and that background processing is to begin.Type: GrantFiled: June 30, 1976Date of Patent: November 1, 1977Assignee: IBM CorporationInventors: Robert William Callahan, Paul Eugene Kauffman, Lawrence Joseph Kobesky, Howard Loomis Page
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Patent number: 4055219Abstract: During the construction of display gas panels front and back panels are connected together by means of a seal which forms a chamber for receiving a display gas. A hole is provided in the back plate which is outside the display viewing area and a glass tube is fitted into this hole and sealed to the assembly. The tube is used to first evacuate and then admit display gas into the chamber. An electric tip-off oven is used to collapse the tube stem to form a permanent seal. A cast protective heat sink and a reflective foil wafer are used to protect the gas panel and the tube-to-gas panel interface from damage by the oven.Type: GrantFiled: June 17, 1974Date of Patent: October 25, 1977Assignee: IBM CorporationInventors: John Victor Orlandi, Neil Myron Poley, Donald Miller Wilson
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Patent number: 4053942Abstract: A device for removing contaminant impurities, particularly contaminants existing at very low levels, from a liquid, including a heating element at least partially immersible in the liquid, a confinement means at least partially immersible in the liquid for maintaining a pulsating bubble of vapor of the liquid, the heating element located within the confining means, openings in the confining means to allow periodic partial escape of the vapor bubble and ingress of liquid.Type: GrantFiled: June 28, 1976Date of Patent: October 11, 1977Assignee: IBM CorporationInventors: William E. Dougherty, Jr., Lawrence V. Gregor, Donald L. Klein, Thomas F. Redmond, Morton D. Reeber