Abstract: A logic gate is disclosed employing enhancement mode MESFET gallium arsenide devices which do not require the tight process control necessary in the prior art because two such devices are employed in the gate circuit to mutually compensate for the effects of their equal deviation from nominal threshold voltages.

Abstract: An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed.

Abstract: Groups of stations operate in TDMA mode relative to associated frequency-separated transponder segments of a satellite repeater. Stations at radio signaling modes in all groups key to a common frame timing reference. The TDMA frame is partitioned repetitively into IN GROUP and CROSS GROUP intervals, each susceptible of containing multiple demand assignable burst time slots. Each node may transmit TDMA bursts (of time compressed and time multiplexed information signals) in assigned slots in either interval (or both). Such bursts are carried only on the transponder radio frequency associated with the respective group. Station receivers are adaptive to switch local oscillator frequencies in synchronism with transitions between IN GROUP and CROSS GROUP periods, and thereby adaptive to receive signals from stations in both groups.

Abstract: In a TDMA satellite communication system, one of the stations is elected the primary station which transmits a reference burst to all other stations to synchronize the local clocks in each station. Each subsidiary station in turn responds by transmitting a local transmit reference burst to enable synchronization of the local transmit clocks. In order to assure that the synchronous operation of the network will continue when the reference station experiences a failure, an alternate reference station is designated in the network which will assume the role of the primary reference station in a baton passing operation in the event that the existing primary reference station must abdicate its reference role. An improved method and apparatus for carrying out the baton passing operation monitors the channel error rate at the reference station and the alternate station.

Abstract: A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Abstract: A randomly accessible memory display is disclosed wherein a latching memory panel can be placed in direct optical contact with the triggering electroluminescent panel having a similar matrix. Once the glowing light from the trigger panel shines on the photosensitive resistive layer providing positive feedback, the corresponding region in the latching memory panel is latched. In accordance with the invention, a technique is disclosed for electrically reading the latched state in any one cell. This is done by selectively propagating a high frequency sinusoidal interrogation signal through each of the Y axis lines connected to the cells and measuring any phase alteration in each of the X axis lines connected to the cells, for each Y axis line interrogated. Since the resistance of the photosensitive resistor for a particular latching cell is altered if that cell is emitting light, the impedance of the cell is changed, thereby introducing a phase shift to the interrogation signal.

Abstract: In vacuum sputter cleaning and plating operations forming a patterned metallic layer on a silicon semiconductor chip, alignment is maintained by anticipating the difference in thermal expansion between the molybdenum mask and the silicon chip and forming the apertures in the molybdenum mask in a radially offset position with respect to the intended cleaning and deposition locations on the semiconductor chip, when the mask and the chip are at room temperature. Then, when the mask and the silicon chip are maintained in a concentric position and are raised to the cleaning and deposition temperature, the differential expansion of the molybdenum mask will bring the apertures therein into perfect alignment with the intended deposition locations on the silicon wafer.

Abstract: A microfilm camera employs a reciprocating lens to optically arrest motion of documents traveling in a high-speed stream for photographic exposure onto stationary, incrementally advanced photographic film. The reciprocation of the lens is controlled by a closed loop servo system. To enhance performance of the servo system, the lens is supported by a four-bar linkage comprising relatively stiff light-weight arms interconnected by crossed leaf spring hinges.

Abstract: A text recorder of the type which includes a text display device to record text in intelligible form on a typewritten page or line or page-like display in response to character and function identifying signals, a keyboard with a plurality of alphabetic, numeric, symbol and function keys for actuation by an operator to produce a keyboard signal unique to the actuated key, decoding means responsive to keyboard signals from said keyboard to produce character and function identifying signals and wherein the decoding means includes a word completion means for producing one of at least two groups of one or more character identifying signals in response to actuation of a selectd key on said keyboard, each group of character identifying signals representing a different word ending and wherein the word completion means includes means for selecting among the group dependent upon the identity of one or more keys actuated prior to actuation of the selected key.

Abstract: A charge coupled device analog-to-digital converter includes a plurality of charge storage stages that are arranged in a serial pipeline register and are connected to pass input source charges from stage to stage down the pipeline register. A reference charge generator and a charge splitter at each stage generate two fixed reference signals. The first of the reference signals is compared by a comparator to a source charge that is temporarily stored at the stage. The comparator generates a binary 1 if the source charge is greater than or equal to the first reference charge and a binary 0 if the source charge is less than the first reference charge. If a binary 1 is generated, only the stored contents of the stage pass to the next successive stage. However, if a binary 0 is generated, the charge contents of the stage is passed to a next successive stage and the second reference charge is also passed by a transfer gate to the next successive stage, where the charges are combined.

Abstract: An automatic erasing typewriter determines, in response to actuation of an erase key, if automatic erasing is possible. If not, the typewriter terminates the erase cycle with a backspace and conditions the typewriter for manual erase. Actuation of a character key as the next actuated key completes the manual erase. Actuation of a key other than a character key deconditions the manual erase.

Abstract: A distributed data processing system is disclosed which has truly distributed control. A plurality of bus interface units (BIU) are interconnected by the distributed system data bus (DSDB) which includes a clock line, a serial command line (CMD), a serial bus allocation line (BAL) and a two byte wide data bus. A central clock connected to the clock line which defines the message frame timing, is the only centralized "control" element in the system. Each BIU may in turn be connected to either one or several data processing units, an I/O port, or a bridge connecting to still another similar bus network.

Abstract: A self-isolated Schottky Barrier diode structure and method of fabrication are disclosed for generating a device having controlled characteristics. An opening is made through an oxide layer over a central region of an n-type semiconductor substrate. The opening has inclined sidewalls over an annular region surrounding the central region of the substrate. An n-type dopant layer is ion implanted through the opening and the surrounding oxide layer. This controls the barrier height for the Schottky Barrier diode and controls the lifetime of minority carriers in the outside region of the substrate. This has the effect of minimizing PNP parasitic transistor action. A Schottky Barrier contact is formed in the opening through an oxide layer creating a rectifying junction with the semiconductor substrate in the central region.

Abstract: In a multiprocessor system, a controllable cache store interface to a shared disk memory employs a plurality of storage partitions whose access is interleaved in a time domain multiplexed manner on a common bus with the shared disk to enable high speed sharing of the disk storage by all of the processors. The communication between each processor and its corresponding cache memory partition can be overlapped with each other and with accesses between the cache memory and the commonly shared disk memory. The addressable cache memory feature overcomes the latency delay which inherently occurs in seeking the beginning of a region to be accessed on the disk drive mass storage.

Abstract: An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed.

Abstract: A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N.sup.- implant is effected between gate electrodes and field oxide insulators, before the N.sup.+ implant. An insulator layer is then deposited also prior to N.sup.+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N.sup.- impurity region during the subsequent N.sup.+ implant. These protected regions are the lightly doped source/drain regions.

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Abstract: A self-isolated Schottky Barrier diode structure and method of fabrication are disclosed for generating a device having controlled characteristics. An opening is made through an oxide layer over a central region of an n-type semiconductor substrate. The opening has inclined sidewalls over an annular region surrounding the central region of the substrate. An n-type dopant layer is ion implanted through the opening and the surrounding oxide layer. This controls the barrier height for the Schottky Barrier diode. In the region of the substrate surrounding the annular region, where the ion implantation takes place through the full thickness of the oxide, the lifetime of minority carriers is controlled. This has the effect of minimizing PNP parasitic transistor action. A Schottky Barrier contact is formed in the opening through the oxide layer creating a rectifying junction with the semiconductor substrate in the central region.

Abstract: A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.

Abstract: A gas laser body, gas laser, a method of manufacture of gas laser body and a method of manufacturing a gas laser are disclosed. The gas laser body comprises a pair of glass plates with means located there between defining a plurality of communicating gas passages. One of said passages comprises a plasma tube. Electrodes may be formed by depositing metal on one or more said plates with said electrodes lying in one or more passages when said plates and means are assembled. The means may comprise another glass plate which has portions thereof cut away to form the gas passages. Alternatively the means may include one or more glass rods suitably shaped to define the gas passages when located between said first and second plates.