Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.

Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.

Abstract: A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel.

Abstract: Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.

Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.

Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

Abstract: Methods and systems for wirelessly transmitting data between Wi-Fi stations without requiring the Wi-Fi stations to be fully connected to the Wi-Fi network. A first Wi-Fi station generates the data to be transmitted. The data comprises status data and/or wake-up data. The first Wi-Fi station then inserts the data in a vendor-specific information element of a probe request frame and wirelessly transmits the probe request frame. The probe request frame is then received by a second Wi-Fi station. If the probe request frame contains wake-up data and the second Wi-Fi station is operating in a low-power mode when it receives the probe request frame, the second Wi-Fi station will wake-up from the low-power mode. If the probe request frame contains status data then the second Wi-Fi station may process the probe request frame and/or forward at least a portion of the received probe request frame to another device.

Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.

Abstract: Apparatus for binning an input value into one of a plurality of bins which collectively represent a histogram of input values, each of the plurality of bins representing a corresponding range of input values, the apparatus comprising: an input for receiving an input value; a noise source configured to generate an error value according to a predetermined noise distribution; and a binning controller configured to mix the received input value with the error value so as to generate a modified input value and to allocate the modified input value to the bin corresponding to that modified input value.

Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.

Abstract: A colour processor for mapping an image from source to destination colour gamuts includes an input for receiving a source image having a plurality of source colour points expressed according to the source gamut; a colour characterizer configured to, for each source colour point in the source image, determine a position of intersection of a curve with the boundary of the destination gamut; and a gamut mapper configured to, for each source colour point in the source image: if the source colour point lies inside the destination gamut, apply a first translation factor to translate the source colour point to a destination colour point within a first range of values; or if the source colour point lies outside the destination gamut, apply a second translation factor, different than the first translation factor, to translate the source colour point to a destination colour point within a second range of values.

Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.

Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.

Abstract: A geometry processing phase of tile-based rendering includes a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to: generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.

Abstract: A method of processing primitives within a tiling unit of a graphics processing system is described. The method comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.

Abstract: A media encoder for encoding a stream of media data blocks has an encoder pipeline including a sequence of processing modules for processing a stream of media data blocks, and a pipeline configurator configured to effect a switch in the encoder pipeline from one or more first encode parameters to one or more second encode parameters. The first processing module of the pipeline can be configured to associate a trigger value with at least a first media data block processed at the first processing module in accordance with second encode parameters, the trigger value passing to subsequent modules so as to cause those modules to adopt the second encode parameters.