Abstract: The presence of an OFDM signal in a received input signal is detected by calculating, for each block of a plurality of blocks of samples of the received input signal, an auto-correlation value at each of a plurality of lags-of-interest; determining, for each of the plurality of lags-of-interest, a rate of growth value across a group of two or more blocks of data samples based on the auto-correlation values; normalising the determined rate of growth values using a normalisation factor to generate normalised rate of growth values; and determining whether an OFDM signal is present in the received input signal based on the normalised rate of growth values.

Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of colour decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).

Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.

Abstract: A pixel filter has a filter module that performs a first recursive filter operation in a first direction through a sequence of pixels to form a first filtered pixel value for each pixel, and performs a second recursive filter operation in a second direction through the sequence of pixels to form a second filtered pixel value for each pixel, the first and second recursive filter operations forming a respective filtered pixel value for a given pixel in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation. The filtered pixel value of the preceding pixel is scaled by a measure of similarity between data associated with that pixel and its preceding pixel. Filter logic combines the first and second filtered pixel values formed by the first and second recursive filter operations to generate a filter output for the pixel, for each pixel of the sequence.

Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.

Abstract: A method of transmitting a stream of packets over a network, the method comprising the steps of: a transmitting device maintaining a measure of network quality; analyzing the measure of network quality so as to determine whether the bandwidth of the network is degrading, beyond a predetermined threshold, the network quality for a transmission over the network; the transmitting device determining a transmission bitrate and a proportion of redundancy in dependence on the analysis; the transmitting device packetising media data and redundancy data in dependence on the determined proportion to generate a stream of packets; and the transmitting device transmitting the generated stream at a rate commensurate with the determined transmission bitrate.

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs.

Abstract: Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set of input data elements and produce results. These results can be that the data elements can be categorized into different subsets, where each subset requires different processing as a next step. The data elements of these different subsets can be coalesced so that they are contiguous in a results set. The results set can be used to schedule additional computation, and if there are empty locations of a scheduling vector (after accounting for the members of a given subset), then those empty locations can be filled with other data elements that require the same further processing as that subset.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.

Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.

Abstract: A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel.

Abstract: Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.

Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.

Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

Abstract: Methods and systems for wirelessly transmitting data between Wi-Fi stations without requiring the Wi-Fi stations to be fully connected to the Wi-Fi network. A first Wi-Fi station generates the data to be transmitted. The data comprises status data and/or wake-up data. The first Wi-Fi station then inserts the data in a vendor-specific information element of a probe request frame and wirelessly transmits the probe request frame. The probe request frame is then received by a second Wi-Fi station. If the probe request frame contains wake-up data and the second Wi-Fi station is operating in a low-power mode when it receives the probe request frame, the second Wi-Fi station will wake-up from the low-power mode. If the probe request frame contains status data then the second Wi-Fi station may process the probe request frame and/or forward at least a portion of the received probe request frame to another device.