Patents Assigned to Imagination Technologies
  • Patent number: 10693513
    Abstract: An IQ amplitude balance estimator is described herein which uses a positive frequency mixer to generate two outputs. The first output is the standard output from a positive frequency mixer and the second output corresponds to a spectrum inverted output from a negative frequency mixer. The second output is generated, however, using the same partial products as the first output and no negative frequency mixer is used. An IQ amplitude imbalance metric is generated by taking the real part of the output from correlation logic which performs a correlation of the two outputs from the mixer. This metric may then be used in a closed loop to compensate for any IQ amplitude imbalance.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 23, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Adrian John Anderson
  • Patent number: 10686942
    Abstract: A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that echo estimate from a microphone signal to output an echo cancelled signal, the gain control system comprising a monitoring unit configured to estimate an energy associated with an impulse response of an adaptive filter configured to generate the echo estimate from the far-end signal and a gain tuner configured to adjust an attenuation of at least one of the microphone signal and the far-end signal in dependence on the estimated energy.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 16, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Gandhi Namani, Srinivas Akella, Sai Ravi Teja Pulugurtha
  • Patent number: 10685483
    Abstract: Viewport transformation modules for use in a three-dimensional rendering system wherein vertices are received from an application in a strip. The viewport transformation modules include a fetch module configured to read from a vertex buffer: untransformed coordinate data for a vertex in a strip; information identifying a viewport associated with the vertex; and information identifying a viewport associated with one or more other vertices in the strip. The one or more other vertices in the strip are selected based on a provoking vertex of a primitive to be formed by the vertices in the strip and a number of vertices in the primitive. The viewport transformation modules also include a processing module that performs a viewport transformation on the untransformed coordinate data based on each of the identified viewports to generate transformed coordinate data for each identified viewport; and a write module that writes the transformed coordinate data for each identified viewport to the vertex buffer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 16, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Jairaj Dave
  • Patent number: 10685420
    Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 16, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Steven J. Fishwick, John W. Howson
  • Patent number: 10679405
    Abstract: Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Jens Fursund, Luke T. Peterson
  • Patent number: 10680657
    Abstract: A data processing device comprising: a jitter buffer for receiving data packets; a media decoder configured to decode the data packets so as to form a stream of media frames, each frame comprising a plurality of samples; a media consumer having an input buffer for receiving the stream of media frames and being configured to play media frames from the input buffer according to a first frame rate; a buffer interface configured to monitor the input buffer so as to detect when the number of samples at the input buffer of the media consumer falls below a predetermined level and, in response, generate a play-out request; and a media controller configured to, responsive to each of the generated play-out requests, play-out one or more data packets to the media decoder so as to cause media frames of the stream to be delivered into the input buffer at a rate commensurate with the first frame rate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Bala Manikya Prasad Puram, Harish Rajamani
  • Patent number: 10679363
    Abstract: A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Marc Vivet, Paul Brasnett
  • Patent number: 10680793
    Abstract: A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Ravichandra Giriyappa, Vinayak Prasad, Oana Rosu
  • Patent number: 10679319
    Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
  • Patent number: 10679322
    Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 9, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Jonathan Redshaw
  • Patent number: 10674162
    Abstract: Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. A decoder unit identifies neighbouring pixels based on coordinates of a sample position and fetches encoded data from the compressed image data for each of the neighbouring pixels. A first decoder decodes fetched encoded blocks of a first image and a difference decoder decodes fetched encoded sub-blocks of differences between the first image and a second image and outputs a difference quad and a prediction value for each of the four pixels, and a reconstruction of the image is generated at the sample position using the decoded blocks of the first image, difference quads and prediction values. A bilinear filtering unit performs bilinear filtering on a linearly interpolated output of a pre-filter using a second part of the coordinates of the sample position to generate the reconstruction of the image at the sample position.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 2, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Rostam King
  • Patent number: 10672183
    Abstract: Graphics processing systems can include lighting effects when rendering images. “Light probes” are directional representations of lighting at particular probe positions in the space of a scene which is being rendered. Light probes can be determined iteratively, which can allow them to be determined dynamically, in real-time over a sequence of frames. Once the light probes have been determined for a frame then the lighting at a pixel can be determined based on the lighting at the nearby light probe positions. Pixels can then be shaded based on the lighting determined for the pixel positions.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 2, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Jens Fursund, Luke T. Peterson
  • Patent number: 10671699
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Anthony Wood, Philip Chambers
  • Patent number: 10665009
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 26, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 10657050
    Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 19, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
  • Patent number: 10657700
    Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
  • Patent number: 10642578
    Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h?1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Tim Lee
  • Patent number: 10636195
    Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Yoong Chert Foo, Kenneth Rovers
  • Patent number: 10638343
    Abstract: A method of estimating the proximity of a first device to a second device in a network causes the first device to perform a first measurement in a first period during which a control message broadcasted over the network instructs devices in the network to not transmit during the first period, wherein the second device disregards the control message and transmits a first signal during the first period which is measured by the first device during the first period, and forms a measure of the proximity of the first device to the second device in dependence on a strength of the first signal.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 28, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Ian Knowles
  • Patent number: 10630683
    Abstract: In an aspect, a wireless communication between a transmitter and a receiver involves determining updated keys according to a key management process for MAC layer encryption. Such key is propagated to a transmitter MAC and though a receiver key management process to a receiver MAC. After a delay, transmitter MAC device begins using the updated key, instead of a prior key, for payload encryption. Receiver MAC continues to use the prior key until a packet that was accurately received fails a message integrity/authentication check. Then, the receiver MAC swaps in the updated key and continues to process received packets. The packet data that failed the message integrity check is discarded. Transmitter MAC retries the failed packet at a later time, and if the packet was accurately received and was encrypted by the transmitter MAC using the updated key, then the receiver will determine that the message is authentic and will receive it and acknowledge it.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 21, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Chakra Parvathaneni