Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.

Abstract: A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a predetermined distance above the plane. The method also includes laterally offsetting the first conductor by a predetermined distance from a region of maximum actuation liability. The region of maximum actuation liability is where an attraction force to be applied to activate the device is at a minimum.

Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C, thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.

Abstract: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: An optical fiber and method of making the same, the optical fiber being characterized by an axial symmetry and comprising a core, doped with phosphorescent or fluorescent impurities, and a transparent envelope. The transparent envelope comprises a cladding layer and optionally a jacket layer surrounding the cladding layer. The optical fiber may further comprise an associated light source comprising an inner electrode, an outer electrode, and an active area, located between said inner electrode and said outer electrode. The light source and said optical fiber are integrated as a unit. The light source is characterized by an axial symmetry and is positioned coaxial with respect to the axis of the optical fiber. The inner electrode is substantially transparent, such that light generated in said active area may propagate outside said light source and into the optical fiber.

Abstract: A method of controlling an internal stress in a polycrystalline silicon-germanium layer deposited on a substrate. The method includes selecting a deposition pressure that is at or below atmospheric pressure and selecting a deposition temperature that is no greater than 700° C. The deposition pressure and the deposition temperature are selected so as to achieve an internal stress in the silicon-germanium layer that is within a predetermined range.

Abstract: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic memory cell with less variation in switching fields, more spatially coherent dynamical magnetic properties for high speed and processional or coherent magnetic switching, and higher signal due to the increased uniformity. It may provide a magnetic sensor with more spatially coherent magnetic properties for high speed and processional or coherent magnetic switching, and increased signal. It may provide a read head element with more spatially coherent magnetic properties for high speed and processional or coherent magnetic sensing, and increased signal.

Abstract: An optical waveguide to fiber coupler comprises a substrate, a first waveguide and a second waveguide. The first and second waveguides are formed on the substrate and intersect at a right angle. A diffraction grating structure is formed at the intersection of the first and second waveguides, such that, when the coupler is physically abutted with a single mode optical fiber, in operation, a polarization split is obtained that couples orthogonal modes from the single-mode optical fiber into single identical modes in the first and second waveguides. Also, employing the coupler in optical polarization diverse applications provides for implementing a polarization insensitive photonic integrated circuit using such diffraction grating structures, such as, for example, photonic crystals.

Abstract: A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.

Abstract: Alternative laser structures, which have potentially the same tuning performance as (S)SG-DBR and GCSR lasers, and a fabrication process which is similar to that of the (S)SG-DBR laser, are presented. The advantage of these structures is that the output power does not pass through a long passive region.

Abstract: The invention relates to a method of optimizing an alignment strategy for processing batches of substrates in a lithographic projection apparatus. First, all substrates in a plurality of batches of substrates in the lithographic projection apparatus are sequentially aligned and exposed using a predefined alignment strategy. Then, alignment data is determined for each substrate in the plurality of batches of substrates. Next, at least one substrate in each batch of substrates is selected to render a set of selected substrates comprising at least one substrate in each batch. In a metrology tool, overlay data for each of the selected substrates is determined. Then, overlay indicator values for a predefined overlay indicator are calculated for the predefined alignment strategy and for other possible alignment strategies. In this calculation, the alignment data and the overlay data of the selected substrates is used.

Abstract: The present invention discloses the formation of a hard mask layer in an organic polymer layer by modifying at least locally the chemical composition of a part of said exposed organic low-k polymer. This modification starts from an exposed surface of the polymer and extends into the polymer thereby increasing the chemical resistance of the modified part of the polymer. As a result, this modified part can be used as a hard mask or an etch stop layer for plasma etching.

Abstract: The present invention discloses a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world. Faraday induction is used to provide electromagnetic coupling between adjacent computational elements and between the computational elements with interface elements of the quantum system. Therefore the corresponding magnetic flux acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements of the quantum system.

Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.

Abstract: The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas separated by areas which are at a lower level. Each elevated area has at its top surface a first layer of a material which is resistant to Chemical Mechanical Polishing (CMP). The method further comprises depositing a layer of a dielectric on top of the whole of said substrate, thereby filling the gaps between said elevated areas. The method further comprises depositing a second layer of a material which is resistant to CMP on top of the whole of said substrate. The method further comprises removing parts of the second CMP resistant layer and of dielectric layer. The method further comprises performing a CMP step and terminating the CMP step at the location of said first and second CMP resistant layers.

Abstract: The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.

Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

Abstract: In one inventive aspect, a thin film device is manufactured by (a) forming a porous semiconductor layer in the form of a thin film on an original substrate, the formation being immediately followed by (b) separation of the thin film by a lift-off process from the original substrate; (c) transfer of the thin film to a dummy support, the thin film not being attached to the dummy support; (d) fabrication of a device on top of the thin film; and (e) transfer and attachment of said device on said thin film on a foreign substrate.

Abstract: The invention relates to a method for creating transient cavitation comprising the steps of creating gas bubbles having a range of bubble sizes in a liquid, creating an acoustic field and subjecting the liquid to the acoustic field, characterized in that the range of bubble sizes and/or the characteristics of the acoustic field are selected to tune them to each other, thereby controlling transient cavitation in the selected range of bubble sizes. It also relates to an apparatus suitable for performing the method according to the invention.