Patents Assigned to IMEC
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Patent number: 6928751Abstract: An apparatus includes a rotatable chuck for supporting a substrate and a splash guard. The splash guard surrounds the chuck and surrounds a substrate mounted on the chuck. The splash guard has a portion that deflects fluid being flung off the substrate by centrifugal action in a manner so as to not splash back onto the substrate. The splash guard is moveable between a process position in which the upper annular edge of the splash guard extends above the chuck and a substrate on the chuck, and a load/unload position in which the splash guard is tilted so that one side of the upper annular edge is below an upper edge of the chuck. The movement of the splash guard facilitates loading and unloading of a substrate.Type: GrantFiled: June 12, 2002Date of Patent: August 16, 2005Assignees: Goldfinger Technologies, LLC, Interuniversitair Microelektronica Centrum (IMEC)Inventors: Chad M. Hosack, Jeffrey M. Lauerhaas, Mario E. Bran, Raoul Standt, Paul Patel, Yi Wu, Geert Doumen, Paul Mertens
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Patent number: 6917236Abstract: A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.Type: GrantFiled: March 10, 2004Date of Patent: July 12, 2005Assignees: Interuniversitair Micro-Elektronica Centrum (IMEC vzw), Universitait Gent, Asulab S.A.Inventors: Jan Doutreloigne, Joachim Grupp, Rolf Klappert
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Publication number: 20050146401Abstract: A tuneable film bulk acoustic resonator (FBAR) device. The FBAR device includes a bottom electrode, a top electrode and a piezoelectric layer in between the bottom electrode and the top electrode. The piezoelectric layer has a first overlap with the bottom electrode, where the first overlap is defined by a projection of the piezoelectric layer onto the bottom electrode in a direction substantially perpendicular to a plane of the bottom electrode. The FBAR device also includes a first dielectric layer in between the piezoelectric layer and the bottom electrode and a mechanism for reversibly varying an internal impedance of the device, so as to tune a resonant frequency of the FBAR device.Type: ApplicationFiled: December 27, 2004Publication date: July 7, 2005Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventors: Hendrikus Tilmans, Wanling Pan
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Patent number: 6910487Abstract: The present invention is related to a method and apparatus for liquid treating and drying a substrate, such as a semiconductor wafer, the method comprising the step of immersing a substrate or a batch of substrates in a tank filled with a liquid, and removing the substrate(s) through an opening so that a flow of the liquid takes place through the opening during removal of the substrate. Simultaneously with the removal, a reduction of the surface tension of the liquid is caused to take place near the intersection line between the liquid and the substrate. For acquiring such a tensio-active effect, a uniform flow of a gas or vapor is used, or/and a local application of heat. The invention is equally related to an apparatus for performing the method of the invention.Type: GrantFiled: July 9, 2003Date of Patent: June 28, 2005Assignee: IMEC vzwInventors: Paul Mertens, Marc Meuris
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Patent number: 6908856Abstract: The invention relates to a method for the fabrication of a device comprising electrical through hole interconnects. In one embodiment, the method comprises anisotropical dry etching of a patternable dielectric material within a substrate hole. One aspect of the invention provides a novel method for producing via or through hole interconnects between microelectronic elements, which is relatively easy to perform and can be applied relatively cheaply compared to the state of the art. The method should, for instance, be applicable in thin chip technology as MCM (Multi Chip Module) and system in a package (SIP) technology.Type: GrantFiled: April 2, 2004Date of Patent: June 21, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Eric Beyne, Riet Labie
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Patent number: 6906400Abstract: A semiconductor device is provided comprising a semiconductor substrate having on its top a Thin Strain Relaxed Buffer. The Thin Strain Relaxed Buffer consists of a stack of three layers of essentially constant Ge concentration. The three layers include a first epitaxial layer of Si1-xGex, a second epitaxial layer of Si1-xGex:C, and a third epitaxial layer of Si1-xGex on the second epitaxial layer. A method to fabricate such a buffer is also provided.Type: GrantFiled: January 13, 2004Date of Patent: June 14, 2005Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips ElectronicsInventors: Romain Delhougne, Roger Loo, Philippe Meunier-Beillard, Mathieu Caymax
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Patent number: 6904091Abstract: Images are subband transformed to create a plurality of subband images. Each subband image includes a plurality of pixels. Each pixel is represented by a plurality of bits with each bit associated to a certain quantization level. Encoding of an image requires scanning essentially all the bits of essentially all the pixels of the image. While scanning in a particular order, one can exploit dependencies within groups of bits consecutively scanned for encoding purposes. Thus, bits of groups can be encoded together. In a subband and transformed image, the scanning order or scanning curve is defined by indicating in which order the system traverses the several subbands and the several quantization levels. One method is characterized in that the set of scanned bits which will be encoded together, and which thus form a group, bits of at least two different sub-images and at least two different quantization levels are recognized.Type: GrantFiled: March 24, 2000Date of Patent: June 7, 2005Assignees: IMEC VZW, Vrije Universiteit BrusselInventors: Peter Schelkens, Jan Cornelis
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Patent number: 6900140Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.Type: GrantFiled: March 12, 2004Date of Patent: May 31, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Serge Vanhaelemeersch, Mikhail Rodionovich Baklanov
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Patent number: 6897517Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.Type: GrantFiled: June 24, 2003Date of Patent: May 24, 2005Assignees: Interuniversitair Microelektronica Centrum (IMEC), Infineon AGInventors: Jan Van Houdt, Luc Haspeslagh
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Patent number: 6898233Abstract: The programmable modem for digital data of the present invention provides a highly programmable, digital modem implemented in an integrated circuit which can be customized to specific applications. The programmable modem uses spread spectrum techniques and is specifically programmable to alter the parameters of the modem to improve performance. The present invention also provides a systematic method and development kit to provide rapid customization of a modem for a particular application or for rapid specification of a high-performance application specific integrated circuit mode.Type: GrantFiled: September 27, 2002Date of Patent: May 24, 2005Assignees: IMEC vzw, SAIT SystemsInventors: Lieven Philips, Jan Vanhoof, Maryse Wouters, Rik De Wulf, Veerle Derudder, Carl Van Himbeeck, Ivo Bolsens, Hugo De Man, Bert Gyselinckx
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Publication number: 20050093154Abstract: In accordance with an embodiment of the invention, a FinFET device is disclosed which comprises a strained silicon channel layer formed on, at least, the sidewalls of a strain-relaxed silicon-germanium body.Type: ApplicationFiled: July 26, 2004Publication date: May 5, 2005Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventors: Anil Kottantharayil, Roger Loo
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Patent number: 6889275Abstract: A system and method are provided that include determining optimum memory organization in an electronic device, wherein further determined are optimum resource interconnection patterns. One aspect of the system and method includes determining resource, e.g., memories and data paths, interconnection patterns of complex bus structures with switches using system-level information about the data-transfer conflicts. The quantity of memories within an electronic device, the size of the memories and the interconnection between the memories, including the interconnection of the memories with one or more data paths, defines a memory organization of an electronic device. Another aspect of the system and method relates to selecting an optimized memory organization, including selecting an optimized interconnection pattern between the memories and between the memories and the data paths.Type: GrantFiled: April 22, 2002Date of Patent: May 3, 2005Assignee: Interuniversitaire Micro-Elektronica Centrum (IMEC vzw)Inventors: Arnout Vandecappelle, Tycho van Meeuwen, Allert van Zelst, Francky Catthoor
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Patent number: 6885570Abstract: The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug.Type: GrantFiled: November 8, 2002Date of Patent: April 26, 2005Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC vzw), STMicroelectronicsInventors: Dirk Wouters, Jean-Luc Everaert, Judit Lisoni
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Patent number: 6884636Abstract: A method of fabricating an infrared detector, a method of controlling the stress in a polycrystalline SiGE layer and an infrared detector device is disclosed. The method of fabricating includes the steps of forming a sacrificial layer on a substrate; patterning said sacrificial layer; establishing a layer consisting essentially of polycrystalline SiGe on said sacrificial layer; depositing an infrared absorber on said polycrystalline SiGe layer; and thereafter removing the sacrificial layer. The method of controlling the stress in a polycrystalline SiGe layer deposited on a substrate is based on varying the deposition pressure. The infrared detector device comprises an active area and an infrared absorber, wherein the active area comprises a polycrystalline SiGe layer, and is suspended above a substrate.Type: GrantFiled: May 18, 2001Date of Patent: April 26, 2005Assignee: Interuniversitair Micro-Elektronica Centrum (IMEC,vzw)Inventors: Paolo Fiorini, Sherif Sedky, Matty Caymax, Christiaan Baert
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Publication number: 20050079291Abstract: A method for depositing a coating layer on at least a part of a surface of a substrate is described. The method includes supplying a coating substance to at least part of a surface of a substrate. The substrate is subjected to a relative movement with respect to a source of the coating substance. The surface tension of the coating substance is modified, at least locally, at least part of the time while the at least part of the substrate is subjected to the movement. A thickness of the coating layer is influenced by modifying the surface tension of the coating substance.Type: ApplicationFiled: June 30, 2004Publication date: April 14, 2005Applicant: Interuniversitair Microelektronica Centrum (IMEC), a Belgium CorporationInventors: Wim Fyen, Paul Mertens
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Publication number: 20050074960Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.Type: ApplicationFiled: September 30, 2004Publication date: April 7, 2005Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventors: Jean Gueneau de Mussy, Gerald Beyer, Karen Maex
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Publication number: 20050074961Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.Type: ApplicationFiled: September 30, 2004Publication date: April 7, 2005Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.Inventors: Gerald Beyer, Jean Gueneau de Mussy, Karen Maex, Victor Sutcliffe
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Patent number: 6876056Abstract: An interconnect module and a method of manufacturing the same is described comprising: a substrate, an interconnect section formed on the substrate, and a variable passive device section formed on the substrate located laterally adjacent to the interconnect section. The interconnect section has at least two metal interconnect layers separated by a dielectric layer and the variable passive device has at least one moveable element. The moveable element is formed from a metal layer which is formed from the same material and at the same time as one of the two interconnect layers. The moveable element is formed on the dielectric layer and is released by local removal of the dielectric layer. Additional interconnect layers and intermediate dielectric layers may be added.Type: GrantFiled: April 18, 2002Date of Patent: April 5, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Hendrikus Tilmans, Eric Beyne, Henri Jansen, Walter De Raedt
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Publication number: 20050068075Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.Type: ApplicationFiled: August 30, 2004Publication date: March 31, 2005Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventor: Manuel Innocent
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Patent number: 6872295Abstract: The present invention is related to a method for the preparation of a composition for electroplating a copper-containing layer on a substrate. This method makes use of an aqueous solution that has at least: a source of copper Cu(II) ions, an additive to adjust the pH to a predetermined value, and a complexing agent for complexing Cu(II) ions. The complexing agent has the chemical formula: COOR1—COHR2R3 in which R1 is an organic group covalently bound to the carboxylate group (COO), R2 is either hydrogen or an organic group, and R3 is either hydrogen or an organic group. The solution has no reducing agent. The method involves providing electrons from a source not in direct contact with the solution, through transport means that provides the contact between said source and said solution. The present invention is also related to a process for forming a copper-containing layer on a substrate in an electroplating bath prepared according to the foregoing method.Type: GrantFiled: December 12, 2001Date of Patent: March 29, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Roger Palmans, Yuri Lantasov