Abstract: A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

Abstract: A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a “full amplitude” mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a “half amplitude” mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

Abstract: At least one embodiment relates to a method for photolithographic patterning of an organic layer on a substrate. The method includes providing a water-soluble shielding layer over the organic layer. In addition, the method includes providing a photoresist layer on the water-soluble shielding layer. The method also includes photolithographic patterning of the photoresist layer to form a patterned photoresist layer. Further, the method includes etching the water-soluble shielding layer and the organic layer, using the patterned photoresist layer as a mask, to form a patterned water-soluble shielding layer and a patterned organic layer. Still further, the method includes removing the patterned water-soluble shielding layer. The method includes, before providing the water-soluble shielding layer, providing a hydrophobic protection layer having a hydrophobic upper surface on the organic layer.

Abstract: The disclosed technology relates to electrode layers of ion insertion type batteries and to electrode layer materials, wherein the electrode layer materials have a good electronic conductivity and a good ion conductivity, and wherein the electrode layers offer a good rate performance and a high storage capacity. The disclosed technology further relates to ion insertion type battery cells and batteries including such electrode layers, e.g., as an anode. The disclosed technology further relates to methods of forming such electrode layers and to methods for fabricating ion insertion type battery cells and batteries. The electrode layers according to the disclosed technology comprise titanium oxide comprising chlorine and may be deposited by atomic layer deposition at temperatures lower than 150° C.

Abstract: A method is provided for creating an interdigitated pattern for a back-contacted solar cell, including deposition of a first passivation layer stack including a-Si of a first doping type, patterning the first passivation layer stack by using a first dry etching process to create one or more regions including the a-Si of the first doping type and one or more exposed regions of the surface, cleaning the one or more exposed regions of the surface from contaminants remaining from the first dry etching process, and depositing a second passivation layer stack including a-Si of a second doping type different from the first doping type to create the interdigitated pattern together with the patterned first passivation layer stack. The cleaning may include depositing a sacrificial layer at least on the exposed regions of the surface, and removing the sacrificial layer by a second dry etching process, at a temperature not exceeding 250° C.

Abstract: The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly.

Abstract: The disclosure is related to a method for producing at least one semiconductor component coupled to a target substrate, where a coupon comprising one or more constituent layers of the at least one semiconductor component is transferred to the target substrate by transfer printing. The coupon is embedded in a portion of a support layer thereby forming an enlarged coupon provided with solid alignment markers on the underside thereof. Corresponding hollow alignment markers exist on the location of the target substrate where the coupon is to be placed. The alignment markers engage to thereby align the coupon to the target location. The disclosure is equally related to a device assembly obtainable by the method.

Abstract: A sensor device for quantifying luminescent targets configured in an at least one dimensional pattern. The sensor device comprises a detector for obtaining an at least one dimensional pattern of measured signals, wherein the detector is adapted for detecting the luminescence of the luminescent targets, resulting in a measured pattern. The sensor device moreover comprises a processor configured to correlate the measured pattern with at least one reference pattern, so as to generate a measurement signal representative for the quantification of luminescent targets. The at least one reference pattern is a recorded pattern or an expected pattern. A recorded pattern is a pattern which is obtained by the detector before the measured pattern is obtained.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap.

Abstract: A method for forming on a substrate a cross-linked layer for directing the self-assembly of a self-assembling material is provided. The method including: (a) providing a structure having the substrate; (b) providing on the substrate a layer of a photo- and thermally cross-linkable substance which, when crosslinked, is suitable for directing the self-assembly of a self-assembling material; (d) photocrosslinking the cross-linkable substance partially; and (d) cross-linking the substance further thermally, thereby forming the cross-linked layer.

Abstract: A method for manufacturing of a waveguide for guiding an electro-magnetic wave comprising: forming a first waveguide layer, a sacrificial layer and a protection layer on a first wafer, patterning to define a pattern of a first waveguide part and a supporting structure in the first waveguide layer; exposing the sacrificial layer on the first waveguide part while the protection layer still covers the sacrificial layer on the supporting structure; removing the sacrificial layer on the first waveguide part; removing the protection layer; bonding a second wafer to the sacrificial layer of the first wafer such that a second waveguide part is supported by the supporting structure and a gap corresponding to the thickness of the sacrificial layer is formed between the first and second waveguide parts.

Abstract: An example oscillator device comprises (i) an oscillation circuit arranged for generating and outputting an oscillation signal and comprising an active circuit to ensure oscillation is maintained, (ii) a voltage-to-current conversion replica circuit of the active circuit arranged for receiving the oscillation signal and for outputting a current proportional to the oscillation signal, (iii) biasing means arranged to generate a constant bias current to activate the oscillation circuit, and (iv) subtraction means for subtracting the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current which can be used for adapting the oscillation signal's amplitude.

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se

Abstract: A solid-state device for photo detection, in general, of terahertz radiation is disclosed. One aspect is a detector device comprising a body having a photoconductive material, a first antenna element connected to a first portion of the body, and a second antenna element connected to a second portion of the body. The first antenna element and the second antenna element are arranged to induce an electric field in the body in response to an incident signal. Further, the device has a waveguide arranged to couple light into the photoconductive material via a coupling interface between the waveguide and the body, where the coupling interface faces away from the first portion and the second portion of the body and is closer to the first portion than to the second portion.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: An example embodiment relates to a method for making a mask layer. The method may include providing a patterned layer on a substrate, the patterned layer including at least a first set of lines of an organic material of a first nature, the lines having a line height, a first line width roughness, and being separated either by voids or by a material of a second nature. The method may further include infiltrating at least a top portion of the first set of lines with a metal or ceramic material. The method may further include removing the organic material by oxidative plasma etching, thereby forming a second set of lines of metal or ceramic material on the substrate, the second set of lines having a second line width roughness, smaller than the first line width roughness.

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

Abstract: A method for directing a self-assembly of a block copolymer comprising a first and a second block is provided. The method including: providing a substrate comprising at least one concavity therein, the concavity comprising at least a sidewall and a bottom, the bottom having a preferential wetting affinity for the second block with respect to the first block; grafting a first grafting material onto the sidewall, selectively with respect to the bottom, the first grafting material having a preferential wetting affinity for the first block with respect to the second block; grafting a second grafting material onto the bottom and optionally onto the sidewall, the second grafting material having a preferential wetting affinity towards the first block with respect to the second block; and providing the block copolymer on the substrate, at least within the at least one concavity.

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.