Abstract: A sensor for measuring mechanical stress in a layered metallization structure such as the back end of line portion of an integrated circuit die is provided. The sensor operates as a field effect transistor comprising a gate electrode, gate dielectric, channel and source and drain electrodes, wherein the gate electrode is a conductor of a first metallization level and the source and drain electrodes are two interconnect vias, connecting the channel to respective conductors in an adjacent level. At least one of the interconnect vias is formed of a material whereof the electrical resistance is sensitive to mechanical stress in the direction of the via. The sensitivity of the electrical resistance to the mechanical stress is sufficient to facilitate measurement of the stress by reading out the drain current of the transistor. The sensor thereby allows monitoring of stress in the BEOL prior to cracking.

Abstract: A method for etching one or more entities on a semiconductor structure, each entity being made of a material selected from metals and metal nitrides is provided. The method includes the steps of: (a) oxidizing by electrolysis, at a current of at least 0.1 A, a precursor solution comprising chloride anions at a concentration ranging from 0.01 mol/l to 1.0 mol/l, thereby forming an etching solution; (b) providing a semiconductor structure having the one or more entities thereon; and (c) etching at least partially the one or more entities by contacting them with the etching solution.

Abstract: An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

Abstract: At least one embodiment relates to a method fabricating a solid-state battery cell. The method includes forming a plurality of spaced electrically conductive structures on a substrate. Forming the plurality of spaced electrically conductive structures on the substrate includes transforming at least part of a valve metal layer into a template that includes a plurality of spaced channels aligned longitudinally along a first direction. Transforming at least part of the valve metal layer into the template includes a first anodization step, a second anodization step, an etching step in an etching solution, and a deposition step. The method also includes forming a first layer of active electrode material on the plurality of spaced electrically conductive structures, depositing an electrolyte layer over the first layer of active electrode material, and forming a second layer of active electrode material over the electrolyte later.

Abstract: A method for forming a film of an oxide of In, Ga, and Zn, having a spinel crystalline phase comprises providing a substrate in a chamber; providing a sputtering target in said chamber, the target comprising an oxide of In, Ga, and Zn, wherein: In, Ga, and Zn represent together at least 95 at % of the elements other than oxygen, In represents from 0.6 to 44 at % of In, Ga, and Zn, Ga represents from 22 to 66 at % of In, Ga, and Zn, and Zn represents from 20 to 46 at % of In, Ga, and Zn; and forming a film on the substrate, the substrate being at a temperature of from 125° C. to 250° C., by sputtering the target with a sputtering gas comprising O2, the sputtering being performed at a sputtering power of at least 200 W.

Abstract: A method for concurrently forming a first metal electrode (31, 58) on an n-type region of a silicon substrate (10) and a second metal electrode (32, 59) on a p-type region of the silicon substrate, wherein the n-type region and the p-type region are respectively exposed in a first and in a second area, is disclosed. The method comprises: depositing (101) an initial metal layer comprising Ni (33, 53) simultaneously in the first area and in the second area by a Ni immersion plating process using a plating solution; and depositing (102) a further metal layer (34, 54) on the initial metal layer comprising Ni (33, 53) in the first area and in the second area by an electroless metal plating process or by an immersion metal plating process, wherein the plating solution comprises Ni and a predetermined amount of another metal different from Ni.

Abstract: A multimodal imaging system comprises a light source, an image sensor comprising a plurality of pixels, and an optical filter comprising a first filter element and a second filter element. The light source emits partially coherent polarized light, and the first filter element and second filter element are arranged as an array parallel to the image sensor. The first filter element is configured for attenuated transmission of a first light spectrum, which comprises polarized light emitted by the light source, and the second filter element is configured for transmission of a second light spectrum. The image sensor is configured to simultaneously capture light impinging on the image sensor from both the first filter element and the second filter element. Each filter element of the optical filter is configured for transmission of light to a subset of the imager pixels.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

Abstract: A method for localization and monitoring of living being targets in an environment comprise: transmitting (302) a sequence of radio frequency waveforms, the waveforms being a continuous-wave waveform modulated in frequency and/or phase; detecting (304) a sequence of reflected waveforms being reflected by a target and Doppler-shifted due to a movement of the target, forming (306) a sequence of waveform transforms, wherein the waveform transform comprises discretized information in a plurality of range bins, and wherein the information in a single range bin corresponds to reflections occurring at a specific sector in the environment; analyzing (308) information for a single specific sector in a sub-sequence of the sequence of waveform transforms, and determining (310) movement of a target in the specific sector based on the waveform transform information for that specific sector during a time period corresponding to the sub-sequence.

Abstract: Disclosed is a system for estimating arterial blood pressure. The system includes a heartbeat detection module configured to receive an electrocardiogram signal, and detect one or more QRS complexes of the electrocardiogram signal. The system also includes a photoplethysmographic sensor module configured to trigger a light emitter, thereby generating a plurality of samples of a photoplethysmographic signal. Further, the system includes a blood pressure calculation module configured to receive information about the detected one or more QRS complexes and the plurality of photoplethysmographic signal samples, and calculate at least one blood pressure value based on a pulse arrival time period between the electrocardiogram and the photoplethysmographic signal.

Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.

Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

Abstract: A Light Emitting Diode (LED) device, particularly a micro-LED (?LED) device, suitable for a ?LED display is described. The LED device comprises a LED array with a plurality of LEDs 12. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

Abstract: The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

Abstract: The disclosed technology relates generally to integrated circuit structures, and more particularly to a semiconductor fin structure having silicided portions. In an aspect, a semiconductor device including a fin structure and a substrate is disclosed. The fin structure includes a first source/drain region, a second source/drain region, and a channel region. The channel region is arranged between the first source/drain region and the second source/drain region to separate the first source/drain region and the second source/drain region in a length direction of the fin structure. The first source/drain region includes a bottom portion and a top portion, wherein the bottom portion of the first source/drain region is fully silicided and the top portion of the first source/drain region is partly silicided.

Abstract: A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlxGa1-xN layer and the second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other and 0?x?1, 0?y?1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980° C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040° C. or lower and is grown to a thickness of 1 ?m or smaller.

Abstract: A method and system for inspection of an item, and a use thereof, are presented. The method comprises acquiring a plurality of projection images of an item at a plurality of projection angles for performing a tomographic reconstruction of the item. A plurality of objects are detected in the tomographic reconstruction and each object has a generic shape described by a parametric three-dimensional numerical model. Said detection comprises determining initial estimates of position and/or orientation of each object and at least one geometrical parameter of the three-dimensional model for each object. The initial estimates are iteratively refining by using a projection-matching approach, in which forward projection images are simulated for the objects according to operating parameters of the radiation imaging device and a difference metric between acquired projection images and simulated forward projection images is reduced at each iteration step.

Abstract: A method for producing an image sensor comprises: depositing a first back-end-of-line, BEOL, layer above a substrate comprising an array of light-detecting elements, said BEOL layer comprising metal wirings being arranged to form connections to components on the substrate and together with depositing the first BEOL layer, improving planarization of the first BEOL layer by depositing a planarizing metal dummy pattern in the first BEOL layer, wherein a part of the planarizing metal dummy pattern is arranged above a light-detecting element, wherein the planarizing metal dummy patterns is formed from the same material as the metal wirings and is deposited to planarize density of the metal deposited in the first BEOL layer across a surface of the layer and wherein a shape and/or position of the metal dummy pattern above the array of light-detecting elements is designed to provide a desired effect on incident light.

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.