Abstract: A method for calibrating an image sensor begins by illuminating a portion of the image sensor with an input light spectrum, where the input light spectrum includes light of known wavelength and intensity. The method continues by sampling an output for each optical sensor of the image sensor, where each optical sensor is associated with one or more optical filters and where each optical filter being associated with a group of optical filters of a plurality of groups of optical filters. Each optical filter of a group of optical filters is configured to pass light in a different wavelength range and at least some optical filters in different groups of the plurality of groups of optical filters are configured to pass light in substantially a same wavelength range.

Abstract: A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.

Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

Abstract: A solid electrolyte (10) of the present disclosure includes: a porous dielectric (11) having a plurality of pores (12) interconnected mutually; an electrolyte (13) including a metal salt and at least one selected from the group consisting of an ionic compound and a bipolar compound, the electrolyte (13) at least partially filling an interior of each of the plurality of pores (12); and a surface adsorption layer (15) adsorbed on inner surfaces of the plurality of pores (12) to induce polarization. The surface adsorption layer (15) may include water adsorbed on the inner surfaces of the plurality of pores (12). The surface adsorption layer (15) may include a polyether adsorbed on the inner surfaces of the plurality of pores (12).

Abstract: The disclosed technology generally relates to silicon solar cells and more particularly to a doped layer formed on a textured surface of a silicon solar cell, and methods of fabricating the same. In one aspect, a method of creating a doped layer at a rear side of a crystalline silicon bifacial solar cell is disclosed. The method can include texturing at least a rear side of a silicon substrate of the solar cell to create a pattern of pyramids, thereby creating a pyramidal topology of the rear side. The method can also include forming a doped layer at the rear side by, using epitaxial growth, growing at least one doped silicon epitaxial layer on the pyramids. Simultaneously with forming the doped layer and by using facet evolution, the pyramidal topology of the rear side can be smoothed by the growth of the at least one epitaxial layer.

Abstract: The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

Abstract: A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.

Abstract: The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component.

Abstract: Disclosed is a quantum-confined Stark effect (QCSE) modulator. In the modulator, a first doped semiconductor region has a first type conductivity, is at the bottom of a trench in a dielectric layer and is immediately adjacent to a semiconductor layer. An MQW region is in the trench on the first doped semiconductor region and at least upper segments of sidewalls of the MQW region are angled away from adjacent sidewalls of the trench such that there are spaces between the MQW region and the dielectric layer. Dielectric spacers fill the spaces. A second doped semiconductor region has a second type conductivity, is on top of the MQW region and optionally extends laterally onto the tops of the dielectric spacers. The spacers prevent shorting of the doped semiconductor regions. Also disclosed are embodiments of a photonics structure including the modulator and of methods for forming the modulator and the photonics structure.

Abstract: A method is provided for obtaining one or more Light Emitting Diode (LED) devices reconstituted over a carrier substrate. The method includes providing a silicon-based semiconductor substrate as the carrier substrate; providing, per each of the one or more LED devices, a compound semiconductor stack including an LED layer; applying a SiCN layer to the stack and the substrate, respectively; bonding the stack to the substrate, wherein the SiCN layer applied to the stack and the SiCN layer applied to the substrate are contacted; and annealing, after bonding, the bonded stack and substrate at a temperature equal to or higher than a processing temperature for completing the LED device from the stack, wherein said temperatures are at least 400° C. A semiconductor structure including the one or more LED devices reconstituted over a carrier substrate is also provided.

Abstract: A method is disclosed for group ranging in a wireless network. The wireless network comprises a plurality of nodes, including an initiator node and a plurality of responder nodes. The method includes performing, for each frequency in a plurality of frequencies, a measurement procedure involving a two-way phase measurement between the initiator node and each of the responder nodes. The measurement procedure includes the initiator node transmitting a carrier signal having the frequency, each responder node of the plurality of responder nodes receiving and performing a phase measurement of the carrier signal, each responder node of the plurality of responder nodes transmitting a carrier signal having the frequency, and the initiator node receiving and performing a phase measurement of the carrier signal. The method further includes calculating, between the initiator node and each responder node of the plurality of responder nodes, a distance, based on the performed two-way phase measurements.

Abstract: The disclosed technology generally relates to superconducting devices, and more particularly to superconducting rings, qubits comprising the superconducting rings and methods of coherently coupling flux states of the superconducting rings. In one aspect, a qubit includes a superconducting ring around a hole. The qubit additionally includes an electric field generator adapted for applying an electric field in a plane of the superconducting ring over at least part of the superconducting ring, and a magnetic field generator adapted for applying a magnetic field component orthogonal to the plane of the superconducting ring such that the magnetic field component at least crosses the hole of the ring.

Abstract: A method of detecting a vital sign comprising at least one of a heart rate and a respiratory rate of a subject is provided. In one aspect, the method includes transmitting a radio frequency signal towards the subject; and receiving a reflected signal from the subject, wherein the transmitted signal is reflected by the subject and Doppler-shifted due to at least one of the heart rate and the respiratory rate to form the reflected signal. The method also includes mixing the reflected signal with a first reference signal; and providing a vital sign carrying signal based on the mixing to a first input of a phase or frequency comparator. The method further includes generating an adjustable second reference signal and providing the reference signal to a second input of the phase or frequency comparator; and generating an output signal, by the phase or frequency comparator.

Abstract: This disclosed technology generally relates to a semiconductor device. One aspect relates to a method of fabricating a stacked semiconductor including forming a semiconductor structure protruding above the substrate and a gate structure extending across the semiconductor structure. The semiconductor structure includes a lower channel layer formed of a first material, an intermediate layer formed of a second material and an upper channel layer formed of a third material. The method additionally includes forming oxidized end portions defining second spacers on end surfaces of an upper layer. And forming the oxidized end portions comprises oxidizing end portions of the upper channel layer at opposite sides of the gate structure using an oxidization process adapted to cause a rate of oxidation of the third material which is greater than a rate of oxidation of the first material, while first spacers cover intermediate end surfaces.

Abstract: A micro-fluidic device is described. The micro-fluidic device includes a semiconductor substrate; at least one micro-reactor in the semiconductor substrate; one or more micro-fluidic channels in the semiconductor substrate, connected to the at least one micro-reactor; a cover layer bonded to the semiconductor substrate for sealing the one or more micro-fluidic channels; and at least one through-substrate trench surrounding the at least one micro-reactor and the one or more micro-fluidic channels.

Abstract: In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.

Abstract: Example embodiments relate to methods for producing a probe suitable for scanning probe microscopy. One embodiment includes a method for producing a probe tip suitable for scanning probe microscopy. The method includes producing a probe tip body that includes at least an outer layer of a probe material. The method also includes, during the production of the probe tip body or after the production, forming a mask layer on the outer layer of probe material. Further, the method includes subjecting the probe tip body to a plasma etch procedure. The mask layer acts as an etch mask for the plasma etch procedure. The plasma etch procedure and the etch mask are configured to produce one or more tip portions formed of the probe material. The one or more tip portions are smaller and more pointed than the probe tip body prior to the plasma etch procedure.

Abstract: In one aspect, a method of forming a semiconductor device includes removing a first dummy gate part extending across a first fin within a first gate trench section in an insulating layer, wherein the first dummy gate part is removed selectively to a second dummy gate part extending across a second fin within a second gate trench section in the insulating layer, and wherein each of the first and second fins is formed by a layer stack including a first layer and a second layer on the first layer, the first layer including Si1-xGex and the second layer including Si1-yGey, wherein 0?x?1 and 0?y?1 and x?y.