Abstract: The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.

Abstract: The present disclosure relates to secure broker-mediated data analysis and prediction. One example embodiment includes a method. The method includes receiving, by a managing computing device, a plurality of datasets from client computing devices. The method also includes computing, by the managing computing device, a shared representation based on a shared function having one or more shared parameters. Further, the method includes transmitting, by the managing computing device, the shared representation and other data to the client computing devices. In addition, the method includes, based on the shared representation and the other data, the client computing devices update partial representations and individual functions with one or more individual parameters. Still further, the method includes determining, by the client computing devices, feedback values to provide to the managing computing device.

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

Abstract: At least one embodiment relates to an autofocus method for determining a focal plane for at least one object. The method includes reconstructing a holographic image of the at least one object such as to provide a reconstructed image at a plurality of different focal depths. The reconstructed image includes a real component and an imaginary component. The method also include performing a first edge detection on the real component for at least two depths of the plurality of different focal depths and a second edge detection on the imaginary component for the at least two depths. Further, the method includes obtaining a first measure of clarity for each of the at least two depths based on a first measure of statistical dispersion with respect to the first edge detection and a second measure of clarity.

Abstract: A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. The magnetic buses include at least a first and a second magnetic bus having opposite magnetization orientations with respect to each other, such that a domain wall separating the opposite magnetization states is pinned in the central region.

Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Abstract: Example embodiments relate to methods for detecting defects of a lithographic pattern. One example embodiment includes a method for detecting defects of a lithographic pattern on a semiconductor wafer that includes a plurality of die areas. Each of the die areas has a region of interest (ROI) that includes a plurality of features forming the lithographic pattern. The method includes acquiring an image of at least one of the ROIs. The method also includes removing features touching an edge of the image. Further, the method includes counting a number of remaining features in the image.

Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.

Abstract: A device and method for forming a vertical channel device is disclosed.

Abstract: Example embodiments relate to extreme ultraviolet absorbing alloys. One example embodiment includes an alloy. The alloy includes one or more first elements selected from: a first list consisting of: Ag, Ni, Co, and Fe; and a second list consisting of: Ru, Rh, Pd, Os, Ir, and Pt. The alloy also includes one or more second elements selected from: the first list, if the one or more first elements are not selected from the first list; and a third list consisting of Sb and Te. An atomic ratio between the one or more first elements and the one or more second elements is between 1:1 and 1:5 if the one or more second elements are selected from the third list and between 1:1 and 1:19 if the one or more second elements are not selected from the third list.

Abstract: A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*LSB; B*MSB), analyzing a bit of the digital signal (COUT) and the calibration bit (B*LSB; B*MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*LSB; B*MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.

Abstract: According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.

Abstract: A mask structure and a method for manufacturing a mask structure for a lithography process is provided. The method includes providing a substrate covered with an absorber layer on a side thereof; providing a patterned layer over the absorber layer, the patterned layer comprising at least one opening; and forming at least one assist mask feature in the at least one opening, wherein the at least one assist mask feature is formed by performing a directed self-assembly (DSA) patterning process comprising providing a BCP material in the at least one opening and inducing phase separation of a BCP material into a first component and a second component, the first component being the at least one assist mask feature and being periodically distributed with respect to the second component.