Patents Assigned to IMEC
  • Patent number: 10186459
    Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 22, 2019
    Assignee: IMEC VZW
    Inventors: Roel Gronheid, Vladimir Machkaoutsan
  • Publication number: 20190013395
    Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 10, 2019
    Applicant: IMEC VZW
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Patent number: 10177902
    Abstract: Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Stichting IMEC Nederland
    Inventor: Alex Young
  • Publication number: 20190006301
    Abstract: The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 3, 2019
    Applicant: IMEC VZW
    Inventors: Fabrice Duval, Fumihiro Inoue
  • Patent number: 10170182
    Abstract: The disclosed technology generally relates to memory devices and more particularly to memory devices based on resistance change, and to systems and methods for evaluating states of memory cells of the memory devices. In one aspect, a memory device includes a plurality of memory cells arranged in an array, where each memory cell comprises a memory element configured to be switched between at least two resistance states. The memory device additionally includes a plurality of word lines and a plurality of bit lines crossing each other, where each of the memory cells is formed at a crossing between one of the word lines and one of the bit lines. In the memory device, the memory cells are configured to be connected to a source line. Additionally, each bit line has a bit line capacitance and is configured to store a charge associated with a state of a selected memory element.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventor: Sushil Sakhare
  • Patent number: 10170692
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Gouri Sankar Kar, Jürgen Bömmels, Davide Crotti
  • Patent number: 10170687
    Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Johan Swerts, Mauricio Manfrini, Christoph Adelmann
  • Patent number: 10170450
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
  • Publication number: 20180374837
    Abstract: A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 27, 2018
    Applicant: IMEC VZW
    Inventor: Frederic Lazzarino
  • Patent number: 10164077
    Abstract: The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Adrien Vaysset, Mauricio Manfrini
  • Patent number: 10163714
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 25, 2018
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10159419
    Abstract: In an aspect of the disclosure, a stimulation device includes a probe attached to a first support. The probe includes at least one grating coupler for coupling light into the probe. The device further includes at least one optical source for providing an optical stimulation signal mounted on a second support, and at least one means for detachably attaching the first support to the second support. The position of the at least one optical source is aligned with the position of the at least one grating coupler to allow light emitted from the at least one optical source to be received by the at least one grating coupler.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 25, 2018
    Assignees: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Luis Diego Leon Hoffman, Dries Braeken, Silke Musa
  • Publication number: 20180361381
    Abstract: The present disclosure relates to a fluid analyzing device that includes a sensing device for analyzing a fluid sample. The sensing device includes a microchip configured for sensing the fluid sample, and a closed micro-fluidic component for propagating the fluid sample to the microchip. The fluid sample can be provided to the micro-fluidic component via an inlet of the fluid analyzing device. And a vacuum compartment, which is air-tight connected to the sensing device, can create in the micro-fluidic component a suction force suitable for propagating the fluid sample through the micro-fluidic component.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 20, 2018
    Applicant: IMEC VZW
    Inventors: Peter Peumans, Liesbet Lagae, Paolo Fiorini
  • Publication number: 20180360367
    Abstract: A brain interaction apparatus is provided. The apparatus comprises a plurality of filaments; and a brain invasive launcher having a plurality of launching channels extending in a longitudinal direction between a proximal end and a distal end thereof. Each launching channel is configured for holding one of the plurality of filaments moveably arranged therein. At least one of the plurality of filaments is provided with a steering tip affixed to a distal end thereof. The steering tip comprises a portion tapering in a longitudinal direction of the at least one of the plurality of filaments thereby narrowing toward a distal end of the steering tip. The tapered portion is rotationally asymmetrical about a longitudinal axis of the at least one of the plurality of filaments.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 20, 2018
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D, VIB
    Inventors: Sebastian Haesler, Luis Diego Leon Hoffman
  • Publication number: 20180358223
    Abstract: A method for directing a self-assembly of a block copolymer comprising a first and a second block is provided. The method including: providing a substrate comprising at least one concavity therein, the concavity comprising at least a sidewall and a bottom, the bottom having a preferential wetting affinity for the second block with respect to the first block; grafting a first grafting material onto the sidewall, selectively with respect to the bottom, the first grafting material having a preferential wetting affinity for the first block with respect to the second block; grafting a second grafting material onto the bottom and optionally onto the sidewall, the second grafting material having a preferential wetting affinity towards the first block with respect to the second block; and providing the block copolymer on the substrate, at least within the at least one concavity.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 13, 2018
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventor: Jan Doise
  • Publication number: 20180359706
    Abstract: Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 13, 2018
    Applicants: Panasonic Intellectual Property Management Co., Ltd., Stichting IMEC Nederland
    Inventors: Ming Ding, Peng Zhang, Yan Zhang, Akio Hirata, Akifumi Nagao
  • Publication number: 20180355089
    Abstract: In a first aspect, the present disclosure relates to a method for immobilizing a molecularly imprinted polymer onto a substrate, comprising providing a substrate having an amorphous carbon surface; and grafting the molecularly imprinted polymer onto the amorphous carbon surface.
    Type: Application
    Filed: April 16, 2018
    Publication date: December 13, 2018
    Applicants: IMEC VZW, Universiteit Hasselt
    Inventors: Anitha Ethirajan, Evelien Kellens
  • Patent number: 10153341
    Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 11, 2018
    Assignee: IMEC VZW
    Inventors: Zheng Tao, Boon Teik Chan, Soon Aik Chew
  • Publication number: 20180345287
    Abstract: A micro-fluidic device 100 for performing digital PCR is presented. The device comprises: a semiconductor substrate; a first micro-fluidic channel 104, comprising an inlet 102 and an outlet 103, embedded in the semiconductor substrate; a heating element 101 thermally coupled to the first micro-fluidic channel 104; a droplet generator 107 connected to the inlet 102 of the first micro-fluidic channel 104 for generating droplets and pumping generated droplets at a flow rate into the first micro-fluidic channel 104; characterized in that: the heating element 101 is a single heating element connected to a temperature control unit 111 configured to cycle the temperature of the complete first micro-fluidic channel 104 through at least two temperature values; and wherein the flow rate of the droplet generator 107 is adaptable. Further, a method to perform digital PCR is presented using the micro-fluidic device 100.
    Type: Application
    Filed: August 9, 2018
    Publication date: December 6, 2018
    Applicant: IMEC VZW
    Inventors: Paolo Fiorini, Tim Stakenborg, Frederik Colle
  • Patent number: 10149381
    Abstract: The present disclosure relates to a method of integrating a interposer device with a textile layer, wherein the interposer device is a stretchable interposer device comprising a stretchable electrically conductive structure with at least one contact pad for establishing at least one electrically conductive path towards the textile layer. The interposer device is arranged to be mechanically attached to a textile layer comprising a plurality of yarns, at least one of which is an electrically conductive yarn. An electrical connection is established between the at least one conductive yarn of the textile layer and the at least one contact pad, which electrical connection is established after the interposer device has been mechanically attached to the textile layer.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 4, 2018
    Assignees: IMEC vzw, Universiteit Gent
    Inventors: Bjorn Van Keymeulen, Frederick Bossuyt, Thomas Vervust