Abstract: The disclosure relates to a method for the fabrication of a thin-film solid-state battery with Ni(OH)2 electrode, battery cell, and battery. One example embodiment is a method for fabricating a thin-film solid-state battery cell on a substrate comprising a first current collector layer. The method includes depositing above the first current collector layer a first electrode layer. The first electrode layer is a nanoporous composite layer that includes a plurality of pores having pore walls. The first electrode layer includes a mixture of a dielectric material and an active electrode material. The method also includes depositing above the first electrode layer a porous dielectric layer. The method further includes depositing directly on the porous dielectric layer a second electrode layer. Depositing the second electrode layer includes depositing a porous Ni(OH)2 layer using an electrochemical deposition process.

Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.

Abstract: A sensor for dielectric spectroscopy of a sample is disclosed. The sensor comprises a waveguide inductively loaded with a composite dielectric section which comprises a sample holder and a discontinuity separating the sample holder from the waveguide. The electromagnetic impedance of the composite dielectric section varies gradually, at least along the propagation direction of the waveguide, and at least from the onset of the discontinuity towards the sample holder.

Abstract: A crystal oscillator circuit comprises: a crystal oscillator; and an injection frequency generating circuit, the injection frequency generating circuit being configured to sense a signal of the crystal oscillator and amplify the sensed signal, the injection frequency generating circuit being further configured to inject the amplified signal to the crystal oscillator; wherein the crystal oscillator circuit is configured such that the crystal oscillator receives the amplified signal during an initial start-up period of the crystal oscillator and stops receiving the amplified signal at an end of the initial start-up period.

Abstract: Disclosed is a method for imaging brain activity from a set of ultrasound images I(t) of blood in a brain, wherein a measured spectrum s(P,t,?) is computed at each point P of the ultrasound images, a reference spectrum s(P,?) is determined at each point P, based on measured spectrums at point P, the reference spectrogram having a high frequency edge decaying in a frequency ?min(P) to ?max(P), and a differential intensity is computed as: dI(P,t)=??min(P)?max(P)A(P,?)[s(P,t,?)?s(P,?)]d? wherein A(P,?) is a positive weighting function.

Abstract: A tunable impedance network includes at least one variable impedance bank comprising a plurality of digitally controlled unit cells each connected from at least a first end to a routing wire. The tunable impedance network is provided with selection means arranged for selecting, based on a desired impedance, a corresponding predetermined digital control signal to be supplied to the variable impedance bank to switch-on a corresponding combination of the unit cells. Between each pair of unit cells in the variable impedance bank, a routing wire section is provided having a respective routing impedance. Each of the predetermined digital control signals is provided for switching-on a combination of unit cells in such a way that the routing impedance of the routing wire section is exploited to fine-tune the actual impedance generated by the variable impedance bank.

Abstract: Provided is a DNA chip with micro-channel for DNA analysis, which has a structure in which a silicon layer (chip A) and a plastic layer (chip B) are laminated, wherein the chip A includes at least two PCR reactors connected in series in a micro-channel, and a filter between the PCR reactors, the chip B includes a reagent, a liquid delivery mechanism and a sensor in a micro-channel, and the reagent, liquid delivery mechanism and sensor can be changed according to a kind of an analyte and an object to be detected.

Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure.

Abstract: A system for hand gesture detection is provided, comprising: a wrist wear adapted to be worn about a wrist of a user of the system and including a set of skin electrodes adapted to face the wrist; an impedance measurement circuit adapted to measure at least a first impedance in a first portion of the wrist and a second impedance in a second portion of the wrist which second portion is circumferentially displaced in relation to said first portion, wherein the first impedance is measured via a first electrode group including four skin electrodes of said set of skin electrodes and the second impedance is measured via a second electrode group including four skin electrodes of said set of skin electrodes, and a processing circuit adapted to detect a hand gesture of the user based on the first and the second impedance measured by the impedance measurement circuit.

Abstract: A method of producing a metal-organic framework (MOF) film on a substrate is disclosed, the method comprising providing a substrate having a main surface and forming on said main surface a MOF film using an organometallic compound precursor and at least one organic ligand, wherein each of said organometallic compound precursor and said at least one organic ligand is provided only in vapour phase.

Abstract: At least one embodiment relates to a method for integrating Si1-xGex structures with Si1-x?Gex? structures in a semiconductor device. The method includes providing a device that includes a plurality of Si1-xGex structures, where 0?x<1. The method also includes depositing a layer of GeO2 on a subset of the Si1-xGex structures. Further, the method includes heating at least the subset of Si1-xGex structures at a temperature high enough and for a time long enough to transform the subset of Si1-xGex structures into a subset of Si1-x?Gex? structures with x?>x.

Abstract: Example embodiments relate to systems and methods for heart rate detection with motion artifact reduction. One embodiment includes an electronic system for heart rate detection. The electronic system includes a random sampling sensor module. The random sampling sensor module includes a first sensor circuit configured to provide nonuniform random samples below a Nyquist rate of a photoplethysmographic signal. The random sample sensor module also includes a second sensor circuit configured to provided nonuniform random samples below a Nyquist rate of a motion signal. The motion signal and the photoplethysmographic signals are sampled with an equivalent pattern. The electronic system also includes a heart rate detection module. The heart rate detection module is configured to calculate a heart rave value based on frequencies corresponding to peak powers of calculated power spectral density value sets corresponding to the photoplethysmographic signals in a frequency range of interest.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: Disclosed is a system for estimating arterial blood pressure. The system includes a heartbeat detection module configured to receive an electrocardiogram signal, and detect one or more QRS complexes of the electrocardiogram signal. The system also includes a photoplethysmographic sensor module configured to trigger a light emitter, thereby generating a plurality of samples of a photoplethysmographic signal. Further, the system includes a blood pressure calculation module configured to receive information about the detected one or more QRS complexes and the plurality of photoplethysmographic signal samples, and calculate at least one blood pressure value based on a pulse arrival time period between the electrocardiogram and the photoplethysmographic signal.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

Abstract: A biometric sensor that measures biometric information and a biometric analysis system including the biometric sensor are provided. The biometric sensor may include: a light source configured to emit light toward a region of interest of an object under examination, the light being diffused at the region of interest; a collimator that includes a though-hole and is configured to collimate the diffused light received from the region of interest; and a spectrometer configure to analyze the diffused light transmitted by the collimator.

Abstract: A device for calculating an indication of power of a received radio signal is disclosed. In one aspect, the device includes a receiver for receiving a plurality of logarithmic values representing a sequence of measurements of power of the received radio signal, and circuitry for determining a sum of the plurality of logarithmic values. The circuitry includes an adder for pairwise summing of two logarithmic values and a plurality of memory registers. The plurality of memory registers are arranged to store intermediate sums of logarithmic values. The circuitry is arranged to control the adder to sum the plurality of logarithmic values by a recursive procedure such that the first and the second logarithmic value in individual summations of the recursive procedure represent substantially same number of power measurements.

Abstract: The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Abstract: The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.