Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.

Abstract: A device for monitoring the physical activity of a living being is disclosed. In one aspect, there is a data input module configured to receive information about the living being's heart beat rate value, motion intensity and anthropometric characteristics. Further, there is an activity recognition and storage module configured to detect, from information received about the living being's motion intensity, the living being's activity and to store information about the living being's heart beat rate value and the motion intensity associated with that detected activity. Further, there is a heart beat rate analysis module configured to determine, from a plurality of heart beat rate values associated with each detected activity, statistics of the distribution of heart beat rate values for each activity or a subset of activities.

Abstract: Example embodiments relate to image sensors and imaging apparatuses. One embodiment includes an image sensor for acquiring an image of an object. The image sensor includes an array of photo-sensitive areas formed on a substrate. Each photo-sensitive area is a continuous area within the substrate and is configured to detect incident light. The image sensor also includes an array of interference filters. Each inference filter is configured to selectively transmit a wavelength band. The array of interference filters is monolithically integrated on the array of photo-sensitive areas. A plurality of the interference filers is associated with a single photo-sensitive area of the array of photo-sensitive areas. Each interference filter in the plurality of interference filters is configured to selectively transmit a unique wavelength band to the photo-sensitive area and each interference filter in the plurality of interference filters is associated with a respective portion of the single photo-sensitive area.

Abstract: An example embodiment may include an optical system for obtaining radiation coupling between two waveguides positioned in a non-coplanar configuration. The optical system may include a first waveguide positioned in a first plane and a second waveguide positioned in a second plane. The first waveguide may be stacked over the second waveguide at a distance adapted to allow evanescent coupling between the first waveguide and the second waveguide. The first waveguide and the second waveguide may be configured such that the coupling is at least partly tolerant to relative translation or rotation of the first waveguide and the second waveguide with respect to each other.

Abstract: In one aspect, the present disclosure relates to a method. The method includes providing a substrate having a patterned layer thereon, the patterned layer including an opening that exposes the substrate. The method also includes selectively infiltrating the patterned layer with a metal or ceramic material, thereby reducing a dimension of the opening. The opening exposes the substrate after the dimension of the opening is reduced.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a device configured as one or both of a spin wave generator or a spin wave detector. In one aspect, the device includes a magnetostrictive film and a deformation film physically connected to the magnetorestrictive film. The device also includes an acoustic isolation surrounding the magnetostrictive film and the deformation film to form an acoustic resonator. When the device is configured as the spin wave generator, the deformation film is configured to undergo a change physical dimensions in response to an actuation, where the change in the physical dimensions of the deformation film induces a mechanical stress in the magnetostrictive film to cause a change in the magnetization of the magnetostrictive film.

Abstract: A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×1018 at/cm3 and, in contact with the lowly doped section, a highly doped section with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 5×1018 at/cm3.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

Abstract: An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlxGayInzN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped Alx?Gay?Inz?N channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlxGayInzN gate layer comprises the steps of: (a1) growing the first part above the p-doped Alx?Gay?Inz?N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3×1019 atoms/cm3, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3×1019 atoms/cm3 and having a top surface having a Mg concentration higher than 6×1019 atoms/cm3.

Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.

Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

Abstract: The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.

Abstract: The present disclosure relates to methods and devices for gas sensing. A gas sensor includes a sensing element comprising at least an ionic liquid. The gas sensor also includes a set of electrodes for polarizing the sensing element and an electric power source for powering the set of electrodes, thus generating an impedimetric response signal from the sensing element. The gas sensor additionally includes readout circuitry for separately analyzing resistive and capacitive components in the impedimetric response signal. A method includes exposing a gas sensor to a gas. The gas sensor includes a sensing element including at least an ionic liquid. The method also includes polarizing the sensing element with an electrical signal at a first frequency, measuring an impedimetric response signal of the sensing element, separating the signal into resistive and capacitive components, and determining the composition of the gas based at least on the resistive and capacitive components.

Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract: A method of producing a metal-organic framework (MOF) film on a substrate is disclosed, the method comprising providing a substrate having a main surface and forming on said main surface a MOF film using an organometallic compound pre-cursor and at least one organic ligand, wherein each of said organometallic compound precursor and said at least one organic ligand is provided only in vapour phase.

Abstract: A method for bonding thin chips to a target substrate is described herein. According to an example method, an adhesive tape is provided with thinned chips attached thereto. The chips are transferred to a carrier substrate by one or more tape-to-tape transfer steps. The carrier is then diced into separate carrier-and-chip assemblies, which can be handled by existing tools designed for handling chips of regular thickness. The fact that the thinning step is separate from the carrier attachment may lead to reduced thickness variation of the chips. The use of tape-to-tape transfer steps allows for attaching either the front or the back side of the chips to the carrier. The use of an individual carrier per chip allows for treating the thinned chip as if it were a standard chip.