Abstract: Provided are a Bragg grating and a spectroscopy device including the same. The Bragg grating is disposed at each of opposite ends of a resonator for reflecting light of a certain wavelength band and includes a core member extending from a waveguide of the resonator in a lengthwise direction of the waveguide; a plurality of first refractive members protruding from the core member and spaced apart from each other along the lengthwise direction; and a second refractive member filling spaces between the first refractive members and having a refractive index different from a refractive index of the first refractive members.

Abstract: A photonics integrated device for coupling radiation using flood illumination is disclosed. The photonic integrated device comprises an integrated waveguide, a coupler grating at the surface of the device for coupling radiation from said flood illumination towards the integrated waveguide, and a grating for blocking, reflecting or redirecting radiation away from the coupler grating at the surface of the device. The grating for blocking, reflecting or redirecting radiation away from the coupler grating thereby is positioned relative to the coupler grating so as to prevent at least some radiation from said flood illumination, impinging at the grating for blocking, reflecting or redirecting radiation away from the coupler grating and thus impinging at a position of said surface away from the coupling grating, from being reflected within the device towards the coupler grating.

Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure.

Abstract: A method for optically and mechanically coupling an optical fiber to an optical or optoelectronic component on a substrate is provided. The method comprises: providing an optical fiber comprising a core and a cladding, the core being exposed at an end face of the optical fiber; forming a polymer waveguide core on the end face, the polymer waveguide core extending from the fiber core; bringing the polymer waveguide core in proximity of the optical or optoelectronic component; providing a liquid optical material, the liquid optical material embedding the polymer waveguide core; and curing the liquid optical material, thereby forming a polymer cladding layer encapsulating the polymer waveguide core and mechanically attaching the optical fiber to the optical or optoelectronic component.

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Abstract: The present disclosure provides a method for defining patterns for conductive paths in a dielectric layer. An example method includes forming a mask layer and forming a set of mandrels, each mandrel having a pair of side wall spacers. The method also includes etching the mask layer to form a first set of trenches in the mask layer. The method further includes covering the set of mandrels with a metal oxide planarization layer, the metal oxide planarization layer filling the first set of trenches. The method also includes etching back the metal oxide planarization layer. The method also includes removing the set of mandrels by etching, thereby forming trenches in the metal oxide planarization layer, the trenches extending between the pairs of side wall spacers. The method also includes etching the mask layer to form a second set of trenches in the mask layer.

Abstract: An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.

Abstract: The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.

Abstract: A system and method for the analysis of biopotential signals using motion artifact removal techniques is disclosed. The system includes a motion classification module configured to receive at least one biopotential signal and at least one reference secondary input signal. The motion classification module performs motion artifact classification for determining motion meta-information, comprising a type and/or severity indication about motion phenomena causing artifacts in the biopotential signal. The motion classification module communicates motion meta-information to a motion artifact reduction module configured to remove motion artifacts from the biopotential signal based on the information received from the motion classification module.

Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.

Abstract: The disclosure is related to a method and apparatus for transmission electron microscopy wherein a TEM specimen is subjected to at least one thinning step by scratching at least an area of the specimen with an SPM probe, and wherein the thinned area is subjected to an SPM acquisition step, using the same SPM probe or another probe.

Abstract: Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.

Abstract: The present disclosure relates to semiconductor devices with gate-controlled energy filtering. One example embodiment includes a semiconductor device. The semiconductor device includes a first electrode, a second electrode, and a channel therebetween. The semiconductor device also includes a first interference structure located in the channel. Further, the semiconductor device includes a first gate for controlling a voltage over the first interference structure. The first interference structure is formed to induce a local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is: (1) aligned with a band structure in the semiconductor device to turn the semiconductor device on; and (2) misaligned with the band structure in the semiconductor device to turn the semiconductor device off.

Abstract: A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns. The method for evaluating comprises obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled pattern. The method furthermore comprises obtaining a scattered radiation pattern on the directed self-assembled pattern obtained using the directed self-assembling method characterized by the set of parameter values, thus obtaining scattered radiation pattern results for the directed self-assembled pattern. The method furthermore comprises determining based on the scattered radiation pattern results a qualification score and correlating the qualification score with the set of parameter values.

Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer including CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer including MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

Abstract: The present disclosure relates to a front-end module for a telecommunication device with an EBD circuit comprising a hybrid transformer for coupling via a transmit port to the telecommunication device transmitting a first frequency transmit signal, to an antenna, via a receive port to the telecommunication device receiving a second frequency receive signal, and to a tunable impedance circuit. In a first configuration the EBD circuit is configured to isolate the transmit port from the receive port at the first frequency, and the FEM comprises a first filter at the transmit port for attenuating the transmit signal with a predetermined amount at the second frequency. In a second configuration the EBD circuit is configured to isolate the transmit port from the receive port at the second frequency, and the FEM comprises a second filter at the receive port for attenuating the receive signal a predetermined amount at the first frequency.

Abstract: An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation. The first and second sets of transistors are supplied by the same voltage supply of the amplifier circuit. The semiconductor body of the first set of transistors is connected to a reference potential to lower the threshold voltage.