Abstract: A probe device is described having a substrate and a die on top of the substrate. The die has an array of stimulation/recording sites having at least one stimulation means and at least one recording means. The substrate comprising the die is folded into a cylindrical shape or a shape with a conical cross-section and, therefore, limits damage when it is implanted in tissue to be examined or treated, e.g., the brain of a patient in case of a neuro-probe device for use in deep brain stimulation.

Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.

Abstract: A device for manipulating magnetic or magnetizable objects in a medium is provided. The device has a surface lying in a plane and comprises a set of at least two conductors electrically isolated from each other, wherein the at least two conductors are adapted for both generating a magnetophoresis force for moving the magnetic or magnetizable objects over the surface of the device in a direction substantially parallel to the plane of the surface, and generating a dielectrophoresis force for moving the magnetic or magnetizable objects in a direction substantially perpendicular to the plane of the surface. Also provided is a method for manipulating magnetic or magnetizable objects in a medium. The method uses a combined magnetophoresis and dielectrophoresis actuation principle for controlling in-plane as well as out-of-plane movement of the magnetic or magnetizable objects.

Abstract: A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices.

Abstract: A micro-fluidic device is described. The micro-fluidic device includes a semiconductor substrate; at least one micro-reactor in the semiconductor substrate; one or more micro-fluidic channels in the semiconductor substrate, connected to the at least one micro-reactor; a cover layer bonded to the semiconductor substrate for sealing the one or more micro-fluidic channels; and at least one through-substrate trench surrounding the at least one micro-reactor and the one or more micro-fluidic channels.

Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).

Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.

Abstract: A method of analog beamforming in a wireless communication system is disclosed. The system has a plurality of transmit antennas and receive antennas. In one aspect, the method includes determining information representative of communication channels formed between a transmit antenna and a receive antenna of the plurality of antennas, defining a set of coefficients representing jointly the transmit and the receive beamforming coefficients, determining a beamforming cost function using the information and the set of coefficients, determining an optimized set of coefficients by exploiting the beamforming cost function, and separating the optimized set of coefficients into optimized transmit beamforming coefficients and optimized receive beamforming coefficients.

Abstract: A method and system are described for determining lithographic processing conditions for a lithographic process. After obtaining input, a first optimization is made for illumination source and mask design under conditions of allowing non-rectangular sub-resolution assist features. Thereafter, mask design is optimized in one or more further optimizations for which only rectangular sub-resolution assist features are allowed. The latter results in good lithographic processing while limiting the complexity of the mask design.

Abstract: A probe for recording and/or stimulating brain activity includes a connecting portion and at least one shank extending from the connecting portion. The at least one shank includes a first side, a second side opposed to the first side, and a fin protruding substantially perpendicularly from the second side and running on at least a part of a length of the at least one shank. The first side includes at least one recording and/or stimulating site.

Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.

Abstract: A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid.

Abstract: Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Abstract: A micromachined gyroscope is disclosed comprising a substrate, three masses m1, m2, and m3, configured to oscillate along a first direction x or y, whereby the first mass m1 is mechanically coupled to the substrate, the second mass m2 is mechanically coupled to the first mass m1 and to substrate, and the third mass m3 is mechanically coupled to the second mass m2, whereby the weight and the spring constants k1, k2, k3 of the respective masses m1, m2, and m3 and mechanical couplings k12, k23 are selected, such that, during operation mass m2 oscillates at a frequency substantially above the resonance frequencies of mass m1 and mass m3. The resonance frequency of mass m2 may be at least 2 times, or even 2.5 times, higher than the resonance frequency of mass m1 or m3.

Abstract: A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described.

Abstract: A method is provided for producing a thin substrate with a thickness below 750 microns, comprising providing a mother substrate, the mother substrate having a first main surface and a toughness; inducing a stress with predetermined stress profile in at least a portion of the mother substrate, said portion comprising the thin substrate, the induced stress being locally larger than the toughness of the mother substrate at a first depth under the main surface; such that the thin substrate is released from the mother substrate, wherein the toughness of the mother substrate at the first depth is not lowered prior to inducing the stress. The method can be used in the production of, for example, solar cells.