Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for spread spectrum functionality for a free-running, reference harmonic oscillator. In an exemplary embodiment, an apparatus comprises a reference oscillator adapted to provide a reference signal having a reference frequency; and a spread spectrum controller adapted to control the reference oscillator to generate a spread-spectrum reference signal at a plurality of different reference frequencies during a predetermined or selected time period. An exemplary apparatus may also include a coefficient register adapted to store a plurality of coefficients and a plurality of controlled reactance modules responsive to a corresponding coefficient of the plurality of coefficients to modify an amount of reactance effectively coupled to the reference oscillator.

Abstract: A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Abstract: A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.

Abstract: A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.

Abstract: A Voltage-to-Current converter includes a current mirror having first and second poles, a first transistor coupled between the first pole of the current mirror and a low voltage through a first resistor, a second transistor coupled between the second pole of the current mirror and a low voltage through a second resistor wherein the second resistor is substantially identical with the first resistor, and wherein the output current is dependent on resistance of the first resistor, the input voltage signal applied to the gate of the first transistor, and a reference voltage signal applied to the gate of the second resistor.

Abstract: A system and method are provided for electrostatic discharge (ESD) protection circuit having overshoot and undershoot voltage protection during a power supply ramp-up of the circuit. In a specific embodiment, the ESD protection circuit of the present invention includes an ESD discharge circuit coupled between a power supply node and a ground supply node, a trigger circuit coupled to the ESD discharge circuit, the trigger circuit to turn the ESD discharge circuit on in the presence of a voltage spike during the power supply ramp-up and to turn the ESD discharge circuit off in the absence of a voltage spike during the power supply ramp-up, and a delay circuit coupled between the discharge circuit and the trigger circuit, the delay circuit to slow down the turn-off of the discharge circuit to prevent an overshoot or undershoot voltage condition during the power supply ramp-up of the circuit.

Abstract: A package assembly (18) that is selectively coupled to a burn-in apparatus (228P) during a burn-in process includes a pin-out (20) having an array of contacts (22) including a set of first contacts (222F) and a set of second contacts (222S). The first contacts (222F) are required for the burn-in process, and are each adapted to be in contact with a corresponding contact member (232P) of the burn-in apparatus (228P) during the burn-in process. The second contacts (222S) are not required for the burn-in process. The second contacts (222S) do not contact any of the contact members (232P) during the burn-in process. The contact members (232P) are arranged at a first pitch. In various embodiments, the array of contacts (22) is arranged at a second pitch that is smaller than the first pitch.

Abstract: A switch includes an arbiter that receives a plurality of requests from N input ports, and determines N round robin arbitration option winners by performing N round robin arbitration options on the requests, each of the N round robin arbitration options performed assuming that a different one of the N input ports was a previous round robin arbitration winner. After the actual previous round robin arbitration winner is identified, a current round robin arbitration winner from among the N round robin arbitration option winners is determined by selecting the round robin arbitration option winner in which the assumed previous round robin arbitration winner is the actual previous round robin arbitration winner.

Abstract: A method and apparatus for switching, merging, and demerging data between data communication locations have been disclosed.

Abstract: A method and apparatus for recovering data by a digital audio interface begins by receiving a stream of biphase encoded data. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Abstract: A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.

Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.

Abstract: A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing operations on the data packets. The baseband processor is scalable such that digital signal processors may be added to, or removed from, the baseband processor. Further, the baseband processor is programmable such that the symbol processing operations may be distributed among the digital signal processors.

Abstract: An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).

Abstract: A packet switch arbitration system and method for arbitration in a packet switch. In one aspect, a method of issuing grants to an ingress port is disclosed in which a first grant request and burst signal are activated at an ingress port having more than one word available for transfer through the switch. A first grant is issued to the ingress port on a first interval. A subsequent grant is issued to the ingress port on a subsequent interval, where the subsequent grant is issued before the ingress port has validated the first grant request.

Abstract: A system and method are provided for a folded cascode amplifier circuit that includes a first order high-pass filter coupled to a first bias voltage, a first input signal and a second input signal, the first input signal and the second input signal defining a differential input signal and the first order high-pass filter arranged to establish a first bias output and a second bias output. To amplify the full-spectrum content of the input signal, the amplifier circuit includes a full-spectrum content amplifier coupled between the first input signal, the second input signal and a current source. To amplify the high-frequency content of the input signal to achieve equalization, the amplifier circuit includes a high-frequency content amplifier coupled to the first bias output and the second bias output, the high-frequency content amplifier arranged to amplify the high-frequency content of the differential input signal to achieve equalization.

Abstract: Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations.

Abstract: A novel method and circuit are disclosed for providing an alternate function to a semiconductor device having a normal operating voltage range and an input pin for receiving an input signal of a voltage level within a normal signal voltage range, for selecting an alternate function, whose steps consist of determining, when a voltage is received at the input pin, whether the voltage is within a normal signal voltage range, enabling the performing of a primary function if the signal voltage is within a normal signal voltage range, and initiating an alternate function when the voltage is outside of the normal signal voltage range.

Abstract: An intertwined test specification (ITTS) is used for controlling Automated Test Equipment (ATE) to apply a sequence of stimulus signals to a device under test (DUT) during a stimulus run and to validate returned response signals during a validation run. The ITTS has response validation scripts intertwined with stimulus invoking scripts where the response validation scripts are conditionally executed during the validation run but not during the stimulus invoking run. Response signals are logically associated with unique stimulus identification codes so that appropriate response signals can be matched with corresponding validation scripts even if the response signals are returned out-of-order to the ATE or to a response logging unit interposed between the ATE and the DUT.