Abstract: A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted. Thereby, the method and apparatus of the present invention allows for failure prediction in a device before it happens, allowing for planned outages or workarounds and avoiding system downtime for unplanned repairs.

Abstract: Methods of forming multi-chip semiconductor substrates include forming a first plurality of dicing streets in a first surface of a first semiconductor wafer having a first plurality of bonding sites thereon and forming a second plurality of dicing streets in a first surface of a second semiconductor wafer having a second plurality of bonding sites thereon. The first surfaces of the first and second semiconductor wafers are bonded together so that the first plurality of dicing streets are aligned with the second plurality of dicing streets and the first plurality of bonding sites are matingly received and permanently affixed within the second plurality of bonding sites. A plurality of bonded pairs of semiconductor chips are then formed by planarizing the second surface of the second semiconductor wafer until the second plurality of dicing streets are exposed.

Abstract: On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Abstract: A digital-to-thermometer-code converter is disclosed for converting a digital signal into its thermometer-code equivalent. Embodiments of the digital-to-thermometer-code include a binary-to-control signal converter that generates a column control signal and a row control signal based on a binary input signal, and a control signal-to-thermometer-code decoder that includes an array of decoder circuit blocks coupled to receive the column control signal and the row control signal, wherein each of the decoder circuit blocks determine at least one bit of the thermometer-code output signal based on at least a first bit of the column control signal.

Abstract: The method of the present invention includes loading a selected set of preset parameters into a source device and a sink device of the DisplayPort device of an embedded system. Link training is then performed between the source device and the sink device utilizing the first set of preset parameter and the link status (bit lock, symbol lock and inter-lane alignment) of the DisplayPort device is then read. If the link status indicates that the link training is successful, a link is established between the source device and the sink device, or if the link status indicates that the link training is unsuccessful, a different set of preset parameters is loaded and link training is then performed again. The steps of loading, performing and reading are repeated with each of the plurality of sets of preset parameters until the link status indicates that the link training is successful.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.

Abstract: A packaged integrated circuit device and a circuit board assembly are disclosed that include a semiconductor die and a package substrate that includes a first grid array of contact pads that are electrically coupled to corresponding contact pads on the semiconductor die. The first grid array of contact pads includes a first set of adjacent rows or columns of contact pads that are coupled to a first channel that extends within a ground plane of the package substrate. The first grid array of contact pads includes a second set of adjacent rows or columns of contact pads that are electrically coupled to a second channel that extends within a power plane of the package substrate. The contact pads in the first set of adjacent rows or columns of contact pads directly overlie a portion of the first channel and the contact pads in the second set of adjacent rows or columns of contact pads directly overlie a portion of the second channel.

Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.

Abstract: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with the discharging charging current when the differential input signal has the first state, and charged with the charging current when the differential input signal has the second state, thereby developing a second output control voltage on the second capacitor. An output driver circuit generates a differential output signal in response to the first and second output control voltages. The slew rate of the differential output signal is controlled by the charging and discharging currents.

Abstract: A method and apparatus for analog smooth switch in VCO loading control, in one technique, receiving an input signal to adjust a frequency of an oscillator; activating one or more switches to control a current source/sink based on the received input signal; applying the current source/sink to a capacitor to adjust a voltage on the capacitor; and applying the voltage on the capacitor to one or more switches, each of the one or more switches connected between a load and a stage of the oscillator.

Abstract: Micro-electromechanical devices include a temperature-compensation capacitor and a thin-film bulk acoustic resonator having a first terminal electrically coupled to an electrode of the temperature-compensation capacitor. The temperature-compensation capacitor includes a bimorph beam having a first electrode thereon and a second electrode extending opposite the first electrode. This bimorph beam is configured to yield an increase in spacing between the first and second electrodes in response to an increase in temperature of the micro-electromechanical device. This increase in spacing between the first and second electrodes leads to a decrease in capacitance of the temperature-compensation capacitor. Advantageously, this decrease in capacitance can be used to counteract a negative temperature coefficient of frequency associated with the thin-film bulk acoustic resonator, and thereby render the resonant frequency of the micro-electromechanical device more stable in response to temperature fluctuations.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A method for testing an integrated circuit for potential latchup sites includes applying a voltage to the integrated circuit, measuring a current through the integrated circuit, applying at least one radiation beam to at least one area of the integrated circuit, and detecting an occurrence of a latchup by detecting an increase of the current through the integrated circuit upon applying the at least one radiation beam to the at least one area of the integrated circuit.

Abstract: A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread. In another configuration, a round robin ranking and a priority ranking are determined for the thread indexes. The thread indexes are then ranked according to the round robin ranking and the priority ranking and the highest ranked thread index of a runnable thread is selected as the scheduled thread.

Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n?1, . . . , 0]) and a second n-bit operand (e.g., B[n?1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ? ( ( C i ? ( A 0 + B 0 _ ) + A 0 ? B 0 _ ) ? ( A 1 + B 1 _ ) + A 1 ? B 1 _ ) ? … ? ( A n - 2 + B n - 2 _ ) + A n - 2 ? B n - 2 _ ) ? ( A n - 1 + B n - 1 _ ) + A n - 1 ? B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.

Abstract: A system that includes a host and a peripheral device. The host transmits a packet that includes a command and a flow control field. The peripheral device receives the packet and has the ability to execute the command, wherein the peripheral device can determine whether the command can be processed in a timely manner, and can update the packet's flow control field with flow control data based on the determination. The host receives the updated packet and has the ability to adjust the flow control of subsequent packets to the peripheral device based on the flow control data in the updated packet.

Abstract: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.