Abstract: An arbiter generates an availability signal indicating whether pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of a packet switch. The availability signal also indicates whether each pseudo-port has a hold. A hold on a pseudo-port indicates that the pseudo-port is being held for an input port of the packet switch. Although the packet switch may complete routing of a data packet in progress to an output port of the pseudo-port that has the hold, the packet switch will not initiate routing of a data packet to an output port of the pseudo-port until each output port of the pseudo-port is available. When all the output ports of the pseudo-port are available, the packet switch can route data of a data packet from the input port for which the pseudo-port is being held to each output port of the pseudo-port.

Abstract: An extended range voltage controller oscillator (VCO) circuit for use in a phase-locked loop (PLL) circuit is provided. The VCO circuit includes two additional pairs of varactors which are used to extend the range of the VCO circuit around its center frequency.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a data selector circuit that is enabled to select the content of an address register in an array of address registers, and a comparator electrically coupled to the data selector circuit and enabled to take a first input from the data selector circuit and target address as a second input from a communication packet. The method includes receiving the target address, seeking and locating a matching address in an array of base address registers, directing the packet to the port associated with the matching address, determining the target address to be a valid address by comparing the target address with a limit address associated with the matching base address, and nullifying the match if the target address is greater than the limit address.

Abstract: An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port, this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion.

Abstract: A method for improving the speed and efficiency of transmitting data between two components in which the transmitted data is sent, at least partly, through a serial bus is shown. According to the method, the fields in the data frames being transmitted between the components are of a fixed length regardless of the amount of data that the receiving device can receive at one time. The data bits of the fixed-length frame correspond to the signals accepted as input by the receiving component.

Abstract: Anti-pop circuits are provided for an audio amplifier that uses a power supply voltage and a ground voltage to drive a load with an audio signal that is centered about a virtual analog ground. These anti-pop circuits include a variable resistor and a capacitor that are connected to the audio amplifier to provide a low pass filter. The variable resistor has resistance that varies in response to a voltage level of the virtual analog ground, such as a difference between a voltage level of the power supply voltage and the voltage level of the virtual analog ground. The variable resistor may be a field effect transistor having a gate that is responsive to the differences between the voltage level of the power supply voltage and the voltage level of the virtual analog ground. The capacitor may be a field effect transistor, as well. Related methods are also described.

Abstract: A method and device for handling catastrophic switch routing errors. Upon receiving a communication packet in a packet switching device, a port in the switching device is matched with the destination address of the communication packet and a routing code is generated to direct routing of the communication packet internally to the packet switching device. The routing code is analyzed to determine whether a catastrophic routing condition exists in the routing code. If no catastrophic routing condition exists, the routing is executed. However, when there is a catastrophic routing condition, execution of the routing of the communication packet is prevented.

Abstract: A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Abstract: A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit.

Abstract: A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.

Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

Abstract: A packet switch includes an error management module in addition to various components that facilitate routing of data packets through the packet switch. The components generate error codes indicating errors occurring in the packet switch and provide the error codes to the error management module. The error management module select error codes generated by the components and generates an error log based on the selected error codes. Each component is inhibited from providing the same error code to the error management module more than once until the component receives an acknowledgement for that error code from the error management module. A user can access the error log during operation of the packet switch to monitor performance of the packet switch.

Abstract: A method and apparatus for self gate pumped NMOS high speed switch have been disclosed.

Abstract: An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.

Abstract: An integrated circuit includes a phase step generator and a clock circuit. The phase step generator generates an input clock signal based on a reference clock and the clock circuit generates an output clock signal based on the input clock signal. Additionally, the clock circuit generates a feedback clock signal based on the output clock signal and locks a phase of the feedback clock signal with a phase of the input clock signal. In response to an assertion of a trigger signal, the phase step generator extends a phase of the input clock signal by inserting a phase step into the reference clock signal. A bandwidth of the clock circuit is determined based on the output clock signal after assertion of the trigger signal.

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Abstract: A phase difference detector having concurrent fine and coarse capabilities synchronizes operations of coarse and fine phase detectors. In one embodiment, clusters of fine timing markers are generated by delay stages of a delay locked loop. The K'th one of every cluster of J fine timing markers is designated as a coarse marker. A first timer determines which of J fine markers in a first cluster is closest to a rising edge of a reference signal. A second timer determines which of J fine markers in a second cluster is closest to a rising edge of a follower signal. A third timer determines how many coarse markers separate the rising edges of the reference and follower signals. Temporal displacement values obtained from the determinations of the first though third timers are combined to produce a phase displacement measurement signal of broad range and high precision across its operating range.

Abstract: An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages.

Abstract: An auto-adaptive digital phase locked loop (DPLL) includes a phase detector comprising an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock. The DPLL also includes a programmable first counter that counts down at the generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output that outputs a counter state based on the generated clock and the integer value M. A first register has a first input that receives the reference event, a second input that receives the counter state, and an output that outputs a sample value N(t), wherein the register stores the counter state as the sampled value N(t) that represents a code for a phase between the reference event and the counter state.