Abstract: A method and apparatus for cross-point detection in devices have been disclosed where each leg of a differential signal is compared to a reference voltage and time lags for each are noted in crossing the reference voltage and this information is used to identify characteristics of the differential signal.

Abstract: A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage.

Abstract: A package substrate (16) for electrically connecting an integrated circuit (12) to a printed circuit board (14) includes a core (222c), a patterned conductive layer (220c), a plurality of spaced apart, discrete capacitors (230), and an insulating layer (222b). The patterned conductive layer (220c) is positioned on the core (222c). The discrete capacitors (230) are electrically connected to the patterned conductive layer (220c). The insulating layer (222b) covers the patterned conductive layer (220c) and separates the capacitors (230). The capacitors (230) are positioned to provide a relatively low impedance path for quick access to power to stabilize the voltage delivered to the integrated circuit (12), and the capacitors (230) do not occupy valuable space on the integrated circuit (12), and the printed circuit board (14).

Abstract: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: In one aspect, a negative voltage coefficient resistor is provided. The negative voltage coefficient resistor includes an insulative layer positioned between a polycrystalline silicon resistive layer and a silicide layer. Upon application of an appropriate voltage bias at the silicide layer of the resistor, a tunneling current is established across the insulative layer and is supplied to the polycrystalline silicon resistive layer. The tunneling current limits the current flow through the polycrystalline silicon layer, producing a resistor having a negative voltage coefficient of resistance and a reduced temperature coefficient of resistance.

Abstract: A ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage, while the remaining inverter stages are operated in response to a highly filtered constant input voltage. The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response to the variable input voltage causes the frequency of the output signal to deviate from the base frequency by an amount determined by the variable input voltage. In this manner, the variable voltage inverter stage implements frequency control for the ring oscillator. The gain of the ring oscillator circuit is reduced by a factor of (2N+1) with respect to the gain of a conventional ring oscillator.

Abstract: A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.

Abstract: A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.

Abstract: A method and apparatus for overbooking FIFO memory have been disclosed.

Abstract: A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a multiplexer that is enabled to select content from a base address register in an array of base address registers, a comparator enabled compare a base address in the content with a target address from a packet, and a comparator enabled to concurrently compare a limit address in the content with the target address and the output of the limit address comparator. The method includes receiving the target address, locating a matching base address in an array of base address registers, concurrently comparing the target address with a limit address associated with the matching base address, and indicating if said target address is not valid.

Abstract: A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case pre-clocking is used to allow an output signal more time to reach a given level. In another case a pre-clocking adjustment may be determined while a device is in operation.

Abstract: A switch activator includes a tongue including a first end and a second end and a surrounding portion. The tongue is joined to the surrounding portion at the first end and has a pressing point adjacent the second end. The tongue may be joined by glue, a heat stake or a rivet. Preferably, the tongue and the surrounding portion integrally formed in a surface. This invention provides a very low cost method of actuating a SOCI (State Of Charge Indicator) push-button switch under the requirements of MIL-PRF-49471B, paragraph 4.7.17.

Abstract: Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.

Abstract: A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.

Abstract: A method and apparatus for improved efficiency in protocols using character coding have been disclosed.

Abstract: A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

Abstract: A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor constructs data packets, each including a data portion and the destination address of the data portion. The packet processor then routes each of the constructed data packets based on a destination identifier of the constructed data packet. An external recipient can then store the data portions of the constructed data packets based on the data addresses in the constructed data packets.

Abstract: A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and routes the data packet to the destination port. Additionally, the packet switch selects data packets among the data packets received by the packet switch based on the data payloads of the received data packets, identifies a trace port of the packet switch for each selected data packet, and routes the selected data packet to the trace port.