Abstract: A packet switch includes a pointer table for mapping locations in an input data buffer to locations in an output data buffer. The processor generates an output data packet based on data portions in the input data buffer and based on the pointer table. The output data buffer stores data portions of the output data packet successively in a sequential order and can output the data portions of the output data packet successively in a sequential order. The pointer table may be configured to reduce the latency or reduce the power consumption of the packet switch.

Abstract: A clock circuit generates a reference clock signal based on a resonant frequency of a crystal, generates thermometer-coded signals based on the reference clock signal, and generates a pulse train based on the thermometer-coded signals. The pulse train has a frequency that is a multiple of the frequency of the reference clock signal. Additionally, the clock circuit includes a phase-lock loop for generating an output clock signal based on the pulse train and aligning a phase of the output clock signal with pulses in the pulse train. In various embodiments, the frequency of the reference clock signal is the same as the resonant frequency of the crystal and the frequency of the output clock signal is a multiple of the resonant frequency of the crystal. Moreover, reference clock signal and the output clock signal each have a long-term jitter based on the precision of the resonant frequency of the crystal.

Abstract: A common access ring (CAR) network includes a main ring and one or more sub-rings. The main ring includes one or more masters, one or more slaves, and one or more bridges. Each sub-ring is coupled to the main ring through a corresponding bridge. Each node of the CAR network is assigned a unique identifier, thereby implementing a global flat address space. One or more masters may issue requests on the CAR network, such that multiple transactions are simultaneously pending. Multiple masters may simultaneously issue requests to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. Requests received by busy slaves are returned to the originating masters, and may be subsequently re-sent.

Abstract: A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. If a request arrives while a slave is processing a previous request, the arriving request is not serviced, and the master that originated the arriving request is asked to retry the request at a later time. Atomic shadow-write operations are supported by including all shadow registers in a dedicated sub-ring of the CAR architecture.

Abstract: A plug-in detection module includes an impedance network for producing a plug-in signal in response to a supply signal that varies when one of a plurality of plug-in receptors is coupled to a plug connector and when one of the plurality of plug-in receptors is decoupled. A reference signal generator generates a reference signal having a plurality of reference signal values. A comparator generates a detection signal when the plug-in signal compares favorably to the reference signal. A processing module detects which of the plurality of plug-in receptors have a plug connector coupled thereto.

Abstract: A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port.

Abstract: A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.

Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.

Abstract: A device and method for protecting HDCP cryptographic keys are presented herein. The device and method include receiving a set of HDCP cryptographic keys, encoding the set of HDCP cryptographic keys such that the resultant encoded cryptographic data is enabled to be represented in rows and columns, and storing the set of keys in a storage device of an HDCP appliance in the rows and columns, wherein at least one of the rows does not include a complete cryptographic key and at least one of the columns does not include a complete cryptographic key. The method can use block interleaving or convolution interleaving encoding.

Abstract: A method for forming a semiconductor die and a flip-chip integrated circuit device are disclosed that include a power and ground mesh that is oriented diagonally. A layout of a semiconductor die is formed by generating a first integrated circuit design and copying and rotating the design so as to form three additional integrated circuit design blocks. The power and ground mesh layer includes four overlying sets of power and ground strips that are oriented diagonally and symmetric. Because the power and ground strips of the present invention are angled and correspond to the underlying integrated circuit design, they allow for powering both rotated and non-rotated logic while maintaining identical interconnection points and capacitive loading across all the repeated blocks. In addition, the angled power and ground strips allow for easily coupling power and ground to structures around the periphery of the power and ground strips.

Abstract: Oscillators include a resonator having first and second electrodes and configured to resonate at a first frequency at which the first and second electrodes carry in-phase signals and at a second frequency at which the first and second electrodes carry out-of-phase signals. A driver circuit is configured to selectively sustain either the in-phase signals on the first and second electrodes or the out-of-phase signals on the first and second electrodes so that the resonator selectively resonates at either the first frequency or the second frequency, respectively. Related oscillator operating methods are also disclosed.

Abstract: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result.

Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.

Abstract: A packet switch including input ports and output ports allocates an output bandwidth of each output port among virtual channels based on bandwidth allocations values corresponding to the virtual channels and a bandwidth precision value of the output port. The bandwidth precision value indicates a number of bandwidth precision bits, which may be outside a bandwidth reservation precision range specified in a serial RapidIO standard. The packet switch receives data packets compliant with the serial RapidIO standard at the input ports, identifies an output port for each data packet, and selects input ports based on the output ports of the data packets. Further, the packet switch routes a data packet from each selected input port to the output port of the data packet, and the output port outputs the data packet by using the output bandwidth of the output port allocated to the virtual channel identified by the data packet.

Abstract: A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control configured to indicate whether a predetermined number of edges is present in the set of samples, and a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control. The phase detector is configured to determine a skew condition based on a relation between a threshold and a number of skew errors detected in the set of samples. A value of the threshold is selected according to the indication of the dynamic phase decision control. A lower value of the threshold is selected according to an indication of the dynamic phase decision control that only one edge is present in the set of samples.

Abstract: In PCI-Express and alike network systems, back-up copies of recently sent packets are kept in a replay buffer for resending if the original packet is not well received by an intended destination device. A method for locating the back-up copy in the retry buffer comprises applying a less significant portion of the sequence number of a to-be-retrieved back-up copy to an index table to obtain a start address or other locater indicating where in the retry buffer the to-be-retrieved back-up copy resides. A method for skipping replay of late nullified packets includes deleting from the index table, references to late nullified packets.

Abstract: A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.

Abstract: A method and apparatus for conversion of an arbitration table into count values to control the distribution of resources have been described.

Abstract: A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signal. The harmonic frequency detector includes a counter for generating a first divided clock signal by dividing the frequency of the output clock signal by a first divisor. Additionally, the harmonic frequency detector includes a counter for generating a second divided clock signal by dividing the frequency of the reference clock signal by a second divisor. The harmonic frequency detector also includes a frequency comparator for generating an output indicating whether the frequency of the output clock signal is a harmonic frequency of the frequency of the reference clock signal based on the first divided clock signal and the second divided clock signal.

Abstract: A control circuit includes a phase frequency detector that receives a reference phase ?REF (signal) as an input and a feedback phase ?FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ?FBK (signal). An auxiliary feedback loop receives error phase ?E (signal) from each of the reference phase ?REF (signal) and the feedback phase ?FBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.