Patents Assigned to Integrated Device Technology
  • Publication number: 20060083185
    Abstract: A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 20, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Sibing Wang, Xiaoqian Zhang, Zhonghai Gan, Shubing Zhai
  • Patent number: 7020133
    Abstract: A switch queue predictive protocol (SQPP) includes a packet switching system including: a switch fabric having a cross-point switch, and a plurality of line cards, each coupled to the switch fabric. A cross-point buffer is located at each cross-point of the cross-point switch. The switch fabric also includes a plurality of actual available queue space tables (AAQSTs), each identifying the actual queue space available in a row of the cross-point buffers. Each of the line cards includes an input buffer, an output buffer, and a predicted available queue space table (PAQST) identifying predicted queue space available in a corresponding row of the cross-point buffers. Packet information is transmitted from a source line card to the switch fabric only if available queue space is predicted by the corresponding PAQST. The switch fabric uses the AAQST to update the PAQST after packet information is transmitted to a destination line card.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: March 28, 2006
    Assignee: Integrated Device Technology
    Inventors: Yongdong Zhao, Craig A. Lindahl
  • Patent number: 7016987
    Abstract: A computer system is provided that includes a direct memory access (DMA) controller, a memory control device and a slave device, all coupled to a system bus. The DMA controller is configured to implement fly-by read and fly-by write operations between the memory control device and the slave device. The memory control device and the slave device each include read and write aligners. During a fly-by read, data is read from slave device and aligned to the system bus using a peripheral read aligner. The memory control device re-aligns the data received on the system bus using a write aligner and writes the data to a main memory. During a fly-by write, data is read from the main memory and aligned to the system bus using a read aligner in memory control device. A write aligner in the slave device then re-aligns the data received on the system bus.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 21, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Agha B. Hussain, Jiann Liao, Cesar A. Talledo, Jeffrey Lukanc
  • Patent number: 7016211
    Abstract: A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: March 21, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Kee Park, Robert J. Proebsting
  • Patent number: 7015116
    Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: March 21, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Guo-Qiang (Patrick) Lo, Brian Schorr, Gary Foley, Shih-Ked Lee
  • Patent number: 7006518
    Abstract: A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 28, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Matthew D. Ornes, Gene K. Chui, Chris Norrie
  • Patent number: 7006531
    Abstract: An apparatus and method reduce jitter in SPE data transmitted to a switch fabric. A processor receives STS channel requests from the switch fabric, and retrieves SPE data in buffers assigned to the requested STS channels. The processor loads the SPE data in the PDU of a TDM cell, the TDM cell in the PDU of a PIC, and a length of the SPE data in the header of the PIC. The PIC is then embedded in a CSIX frame that is transmitted to the switch fabric through a CSIX interface. The length of the SPE data in the PIC PDU is variable since the processor retrieves SPE data upon demand from the switch fabric. Thus, even if enough data to fill an entire PDU is not in a channel buffer at the time of a channel request, the available data is transmitted so that the opportunity to transmit available SPE data is not lost.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: February 28, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventor: Gurmohan Singh Samrao
  • Publication number: 20060039284
    Abstract: Disclosed are a method and apparatus for processing a complete burst of data by receiving said complete burst of data, storing the complete burst of data in a memory, associating the complete burst of data with a first logical channel and dispatching an egress burst of data according to one or more complete bursts of data stored in a memory and associated with the first logical channel.
    Type: Application
    Filed: April 11, 2005
    Publication date: February 23, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Shubing Zhai, Yefei Sun, Xiaoqian Zhang, Zhonghai Gan
  • Publication number: 20060028860
    Abstract: Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.
    Type: Application
    Filed: November 23, 2004
    Publication date: February 9, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Tzong-Kwang Yeh
  • Patent number: 6996662
    Abstract: A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: February 7, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael J. Miller, Mark Baumann
  • Patent number: 6993028
    Abstract: An apparatus and method for reordering sequence indicated information units into proper sequence are described. The apparatus includes a double-back shifter receiving sequence indicated information units, and at least one circuit coupled to the double-back shifter to repetitively compare, reorder and shift the sequence indicated information units so as to be in proper sequence when shifted out of the double-back shifter. The method includes repetitively comparing, reordering and shifting sequence indicated information units in a double-back shifter so as to be in proper sequence when shifted out of the double-back shifter.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: January 31, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Matthew D. Ornes, Gene K. Chui, Chris Norrie
  • Publication number: 20060018176
    Abstract: In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation performed from the first queue, thereby creating an adjusted read count pointer. If a re-read operation is to be performed from the first queue, the first read mark value is stored in the read address file. Otherwise, the adjusted first read count pointer is stored in the read address file. Similar operations are performed on the write side of the multi-queue memory system.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo
  • Publication number: 20060020742
    Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M?(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Cheng-Han Wu
  • Publication number: 20060018170
    Abstract: A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Ta-Chung Ma, Lan Lin
  • Publication number: 20060020761
    Abstract: A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Hui Su
  • Publication number: 20060020743
    Abstract: A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Xiaoping Fang
  • Publication number: 20060018177
    Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo
  • Publication number: 20060020741
    Abstract: A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Cheng-Han Wu
  • Publication number: 20060017497
    Abstract: A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit generates a second blanking signal, which has a duration corresponding with the duration of the noise introduced to the read count value, in response to the second clock signal. The read and write count values are latched into read and write blanking registers, respectively, in response to the first and second blanking signals, respectively, effectively filtering the introduced noise prior to a subsequently performed comparison operation.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Jason Mo, Mario Au
  • Patent number: 6987684
    Abstract: Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit that is electrically coupled to the CAM core. The control circuit is configured to support internal error detection and correction operations using modified Hamming code words. These operations are performed without significant impact on the compare bandwidth of the search engine device, even when operations to read entries from the CAM core are performed as foreground operations that may block concurrent search operations. The control circuit may perform the error detection and correction operations by issuing multiple read instructions. These instructions include a first instruction (e.g., error check instruction) to read at least a first entry into the CAM core for the purpose of error detection and then, in response to detecting the first entry as erroneous, issuing a second instruction to read the first entry from the CAM core.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 17, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Kenneth Branth, Kee Park, Scott Yu-Fan Chu, Thomas Diede