Abstract: Methods, apparatus and computer program products for modeling integrated circuits having dense devices therein that experience linewidth (e.g., gate electrodes) reductions during fabrication are provided. For dense devices having electrical paths therein and first and second gate electrodes that overlie the electrical path, operations include determining an electrical gate length of the first gate electrode by evaluating a change in current through the electrical path relative to a change in gate length of the second gate electrode. The operation to determine the electrical gate length of the first gate electrode includes evaluating a change in simulated drain-to-source current through the electrical path relative to a change in the electrical gate length of the second gate electrode.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.

Abstract: Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.

Abstract: A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level.

Abstract: An improved method is provided for etching back a tungsten layer that overlies a titanium nitride adhesion layer on a semiconductor structure. This method includes the steps of: (1) performing a first plasma etchback of the tungsten layer for a first predetermined time period, such that a thin layer of tungsten remains over the adhesion layer at the end of the first plasma etchback, (2) actively or passively cooling the resulting semiconductor structure to a temperature of 35° C. or lower, and then (3) performing a second plasma etchback of the tungsten layer until an endpoint is detected, thereby exposing the adhesion layer. Cooling the semiconductor structure prior to the second plasma etchback ensures that the titanium nitride adhesion layer is at a relatively low temperature during the second plasma etchback. The titanium nitride adhesion layer etches significantly slower at lower temperatures, thereby making it easier to stop the second plasma etchback on the adhesion layer.

Abstract: Content addressable memory (CAM) devices include dual-function check bit cells that can operate as check bit cells to support error detection and correction (EDC) operations or as redundant CAM cells that support column redundancy. Dedicated check bit cells are also provided that have a reduced susceptibility to soft errors relative to adjacent CAM cells. The dedicated check bit cells may also be provided within a global mask cell sub-array to support correction of soft errors within global masks.

Abstract: A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No onboard cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Abstract: Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

Abstract: Delay-locked loops have high bandwidth locking characteristics that are less susceptible process, voltage and temperature (PVT) variations. These DLLs are configured to support transition from a partial feedback loop lock condition to a full feedback loop lock condition during a start-up time interval, in order to insure that a multi-cycle lock condition is established at the time the DLL's clock signal output becomes available. The DLL may include a variable delay line that is responsive to a reference clock signal, an auxiliary phase detector that is electrically coupled to the variable delay line, and a main phase detector that is responsive to the reference clock signal and a feedback clock signal (DLLCLK). The auxiliary phase detector may be an edge-triggered SR-type phase detector and the main phase detector may be a three-state phase frequency detector.

Abstract: CAM devices and methods of operating CAM devices include mapping search word portions to partitions and virtual subpartitions in a CAM core. Some embodiments of the invention can provide, for example, a hybrid CAM device that includes a mapping circuit for implementing such partitioning and virtual subpartitioning that is implemented in memory, such as a random access memory (RAM) or a combination of CAM and RAM, that is integrated with the CAM core. In some embodiments, a CAM device includes a search word input, a CAM core comprising a plurality of CAM cells, and a virtual partitioning circuit that selectively enables a partition in the CAM core for search of a portion of a search word at the search word input responsive to the search word, and that provides a mapping of the search word to a comparand input to the CAM core. The mapping defines a virtual subpartition in the CAM core. The invention may be embodied as apparatus and methods.

Abstract: An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner unit, PCI FIFO, Endian swap logic, and PCI-bus interface unit under the control of a PCI FIFO controller. The PCI-side aligner unit properly aligns the data while communicating data with the memory's bus on a word-at-a-time basis, and communicating data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the memory's bus. The Endian swap logic properly orients the data in big or little Endian orientation. The PCI-bus interface unit communicates data with the PCI-bus on a word-at-a-time basis, and communicates data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the PCI-bus.

Abstract: A self-aligned contact, and a method for fabricating the same, are provided. A conductive element having an overlying hydrogen silsesquioxane (HSQ)-based dielectric cap is formed over a semiconductor substrate. Dielectric sidewall spacers are then formed adjacent to sidewalls of the conductive element and the HSQ-based dielectric cap. A HSQ-based dielectric layer is formed over the resulting structure, and an inter-layer dielectric layer, such as TEOS, is formed over the HSQ-based dielectric layer. The inter-layer dielectric layer is then etched through a mask having an opening located over a sidewall spacer, a portion of the HSQ-based dielectric cap and a portion of the substrate. The etch (which may be a C5F8 based etch) has a high selectivity (e.g., about 20:1) with respect to the HSQ-based dielectric layer, thereby enabling the etch to stop on the HSQ-based dielectric layer. Another etch removes the exposed HSQ-based dielectric layer to expose the substrate.

Abstract: The present invention provides a packaged semiconductor device that includes two semiconductor die. The first semiconductor die is attached to a package substrate using adhesive. A first set of wire bonds electrically connect the first semiconductor die to the package substrate. A first layer of encapsulant extends over the first semiconductor die and over the first set of wire bonds. A second semiconductor die is attached to the first layer of encapsulant using adhesive. A second set of wire bonds electrically connect the second semiconductor die to the package substrate. A second layer of encapsulant extends over the second semiconductor die and over the second set of wire bonds.

Abstract: Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log2N stages of 2-to-1 multiple match gates, where N=2k and k is a positive integer.

Abstract: A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (VBE1?VBE2)/R1+VBE1/R2. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance R3 and a third bipolar transistor that exhibits a third voltage drop VBE3, thereby generating a reference voltage.

Abstract: Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.