Abstract: Content addressable memory (CAM) devices achieve high integration by utilizing one or more CAM arrays that are each partitioned by rows into a CAM cell sub-array and a dedicated mask cell sub-array. Each row of mask cells within the mask cell sub-array can be selectively read during one search operation and then used to globally mask one or more columns of the CAM cell sub-array during a following search operation. Mask assertion circuitry is provided to couple a respective mask cell sub-array to a bit/data line control circuit that drives bit and/or data lines to the CAM cell sub-array during read, write and search operations. The mask cell sub-array and CAM cell sub-array may be segmented arrays that support pipelined search, write and read mask operations.

Abstract: Content addressable memory (CAM) devices according to embodiments of the present invention conserve match line and bit line power when CAM array blocks therein are searched. These CAM array blocks are searched in a pipelined segment-to-segment manner to increase search speed. The pipelined search operations may also be interleaved with write and read operations in an efficient manner that reduces the occurrence of pipeline bubbles.

Abstract: A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

Abstract: An ATM switch for transmitting a multicast ATM cell includes a memory, a control circuit, and a cell memory. The control circuit maintains in the memory a connection table which includes a multicast master entry and one or more multicast member entries associated with the multicast master entry. The cell memory stores one or more ATM cells, including the multicast ATM cell. The multicast master entry holds an address of the cell memory at which the multicast ATM cell is stored. The multicast member entries are linked to each other through a circular double linked list.

Abstract: A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate. The doped layer and well region are maintained at a voltage potential that is between a threshold voltage and a breakdown voltage defined the PN junction formed at their interface. The resulting structure attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.

Abstract: A method for fabricating a MOSFET structure is disclosed. A coating is provided on the upper surface of a gate. Thereafter doped regions are implanted into the substrate. A layer is provided over the MOSFET structure and etched to form spacers. The MOSFET structure is reacted with salicide-forming reactant to produce a salicide MOSFET.

Abstract: Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.

Abstract: Integrated circuit inductors achieve high quality factors by replacing a single conductive strand having a first cross-sectional area with a plurality of conductive strands having a combined second cross-sectional area that is smaller than the first cross-sectional area and a combined periphery that is greater than a periphery of the single conductive strand. The dimensions of the plurality of the conductive strands are greater than a skin depth at a desired operating frequency. This results in slightly higher dc resistance, but significantly lower ac resistance. The conductive strands are electrically coupled in parallel and extend side-by-side across an integrated circuit substrate. These strands include a plurality of crossing strand segments that enable the respective strand to be repeatedly transposed from one side of the plurality of strands to another side of the plurality of strands without electrical interruption.

Abstract: Overvoltage protection circuits include a pass transistor having first and second current carrying terminals electrically connected to an input signal line and an output signal line, respectively, and a voltage clamping circuit. The voltage clamping circuit is electrically connected to a power supply line and a gate of the pass-transistor and dynamically clamps a capacitively bootstrapped voltage at a gate of the pass transistor within a first range so that the output voltage as well as the magnitudes of all gate-to-source, gate-to-drain and drain-to-source voltages across the pass transistor and all transistors within the voltage clamping circuit do not exceed a level in excess of about Vdd when Vin=2Vdd, where Vin equals a voltage of an input signal applied to the input signal line and Vdd equals a power supply voltage on the power supply line.

Abstract: A method for forming a photoresist structure that does not have swelling defects. A layer of low activation energy deep ultraviolet photoresist is disposed over a layer that is to be patterned. A layer of high activation energy deep ultraviolet photoresist is then deposited such that the layer of high activation energy photoresist directly overlies the layer of low activation energy photoresist. The two photoresist layers are then processed by performing exposure, post-exposure bake, and development steps to form a photoresist structure. An etch step is then performed so as to form a patterned layer that does not have swelling defects.

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: An apparatus and a method for reducing layer separation and cracking in semiconductor devices. A structure is formed over a semiconductor wafer that includes die separated by scribe streets and that includes probe pads for testing die. A notch is cut within a scribe street so as to expose an open area that does not contain any probe pad and that does not contain any metal layers. The wafer is then severed into semiconductor devices by extending a cutting blade through the open area. A semiconductor device is then electrically and physically coupled to a ball grid array substrate to form a ball grid array device having reduced layer separation and cracking.

Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: A CAM device includes an array of multi-compare port CAM cells therein. The CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: Content addressable memory (CAM) devices include a first match line segment associated with a first row of CAM cells within a CAM array and an inverter having an input electrically coupled to the first match line segment. A match line precharge support circuit is provided. The match line precharge support circuit includes a first PMOS transistor having a gate terminal electrically coupled to an output of the inverter, a first current carrying terminal that is electrically coupled to the first match line segment and a second current carrying terminal that is electrically coupled to a power supply line.

Abstract: A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration. One implementation of the apparatus includes one or more DMA channel interfaces providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided before a current DMA transfer is completed; and a DMA controller that initiates arbitration of DMA channel requests after they are provided by the one or more DMA channel interfaces and before the current DMA transfer is completed, and initiates set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration.

Abstract: A semiconductor structure is provided that includes a gate, a dielectric spacer located adjacent to a sidewall of the gate, a source/drain region, and a continuous silicide strap located over the gate, the dielectric spacer and the source/drain region. The silicide strap provides an electrical connection between the gate and the source drain region. In one embodiment, the silicide strap is formed by a method that includes the steps of (1) implanting a semiconductor material, such as silicon, into upper surfaces of the gate, the dielectric spacer, and the source/drain region, (2) depositing a refractory metal over the implanted semiconductor material, and (3) reacting the refractory metal with the implanted semiconductor material, thereby forming the continuous silicide strap at the upper surfaces of the gate, the dielectric spacer and the source/drain region. Advantageously, the dielectric spacer does not need to be removed prior to forming the silicide strap.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.