Abstract: Content addressable memory (CAM) devices according to embodiments of the present invention conserve match line and bit line power when CAM array blocks therein are searched. These CAM array blocks are searched in a pipelined segment-to-segment manner to increase search speed. The pipelined search operations may also be interleaved with write and read operations in an efficient manner that reduces the occurrence of pipeline bubbles.

Abstract: A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port.

Abstract: A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate that attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.

Abstract: A self-aligned contact, and a method for fabricating the same, are provided. A conductive element having an overlying hydrogen silsesquioxane (HSQ)-based dielectric cap is formed over a semiconductor substrate. Dielectric sidewall spacers are then formed adjacent to sidewalls of the conductive element and the HSQ-based dielectric cap. A HSQ-based dielectric layer is formed over the resulting structure, and an inter-layer dielectric layer, such as TEOS, is formed over the HSQ-based dielectric layer. The inter-layer dielectric layer is then etched through a mask having an opening located over a sidewall spacer, a portion of the HSQ-based dielectric cap and a portion of the substrate. The etch (which may be a C5F8 based etch) has a high selectivity (e.g., about 20:1) with respect to the HSQ-based dielectric layer, thereby enabling the etch to stop on the HSQ-based dielectric layer. Another etch removes the exposed HSQ-based dielectric layer to expose the substrate.

Abstract: A content addressable memory (CAM) device includes a CAM array that has multiple entries therein that are arranged in groups by weight class. Each entry comprises data bits and independently searchable weight bits that identify the weight class of the entry.

Abstract: Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate structures over a semiconductor substrate. A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a capping nitride layer 30 overlying the conductive layer 28. A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the capping nitride layer 30 at a rate lower than the rate of deposition on the conductive layer 28. Thus, the liner 32 is substantially thinner on the capping nitride layer 30 than on the conductive layer 28. A nitride spacer is formed over 34 the liner 32. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks and substantially free of voids.

Abstract: Physical vapor deposition (PVD) system comprises a chamber, an upper shield and a lower shield mounted within the chamber, a cover ring having one or more tabs extending radially inwardly therefrom. The PAD system further includes a shutter disk having one or more notched areas formed in the periphery thereof to receive non-contacting the one or more tabs of the cover ring. The cover ring has two or more recesses formed in an upper side thereof with a guide pin extending from the center of the recesses. The lower shield has two or more cups with a hole therein to be engaged with the guide pin of the cover ring to keep the lower shield from rotating with respect to the cover ring. The cups of the lower shield are inserted into the recesses of the cover ring. These improvements enable a standard shutter arm assembly and a shutter disk to be utilized in a two-tab block-out scheme.

Abstract: A method for generating a swing curve and a photoresist feature formed using the swing curve. A layer of photoresist is formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of points. The semiconductor wafer is then exposed and developed to form a photoresist structure that includes features. For each of the points at which thickness was determined, the size of a corresponding feature is determined. A curve is then determined that correlates the thickness measurements and the size measurements. The resulting swing curve is then used to determine a thickness for photoresist deposition and a photoresist layer is deposited, exposed, and developed to obtain a photoresist feature having the desired size.

Abstract: A translation circuit for translating addresses between computer networks and an associated method of performing address translation for a computer system are provided. The translation circuit includes a content addressable memory (CAM) device having a CAM array that is logically divided into a plurality of CAM segments. First and second sets of CAM segments are designated to perform comparison operations for addresses having first and second widths, respectively. An instruction provided to the CAM device specifies an address translation having either the first or second width. A comparison operation is performed in the first set of segments if the instruction specifies an address translation of the first width. A comparison operation is performed in the second set of segments if the instruction specifies an address translation of the second width. In one embodiment, each segment has the same size, and includes a plurality of sub-segments, each having the same width.

Abstract: An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit.

Abstract: An integral system for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.

Abstract: Multi-phase clock generators include a master-slave flip flop that generates a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency. The master-slave flip-flop includes a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs. A slave stage is also provided. The slave stage is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled and fed back to the first pair of differential inputs of the master stage.

Abstract: A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh operation, data words and associated check bits are read from the RAM array and transmitted to the EDC circuit. The EDC circuit analyzes each data word and associated check bits to detect errors, and corrects the data word, if necessary, before sending the data word to the CAM array.

Abstract: A method for forming a packaged semiconductor device and a packaged semiconductor device. A first semiconductor die is coupled to a package substrate. Wire bonds are then coupled to the first semiconductor die and to the package substrate. Encapsulant is applied such that the encapsulant extends over the first semiconductor die and over the wire bonds. The encapsulant is then at least partially cured. A second semiconductor die is coupled to the encapsulant. The second semiconductor die is electrically coupled to the ball grid array substrate. Encapsulant is then applied and cured to form a second layer of encapsulant that covers the second semiconductor die.

Abstract: A server is provided having a port for receiving a data request that includes an identifier (e.g., an HTTP request that includes a URL). Recognition logic is provided to extract the identifier, using delimiters present in the data request. Padding logic fixes the length of the identifier at a predetermined length (e.g., by adding zeros to the end of the identifier), thereby creating a fixed-length identifier. Hashing logic is provided to perform a hashing function on the fixed-length identifier, thereby creating a hashed identifier. A CAM array provides an index value in response to the hashed identifier if the hashed identifier matches a hashed identifier value stored in the CAM array. A cache memory stores information associated with the identifier (e.g., web page data), at a location associated with the index value. The cache memory provides this information to a requesting party in response to the index value.

Abstract: An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value matches an entry of the binary CAM array. In a particular embodiment, the hardware hashing circuit can be configured to process character strings having different lengths (greater than the width of the binary CAM array) in response to one or more configuration bits. The hardware hashing circuit can include, an input register, Data Encryption Standard (DES) circuitry and exclusive OR circuitry.

Abstract: A deficit round-robin scheduler including a round-robin table configured to store a plurality of cycle link lists, wherein each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries, wherein each of the flow table entries is associated with a corresponding flow, and therefore has a corresponding FLID value. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The deficit round-robin scheduler also included an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.

Abstract: Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.

Abstract: An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Abstract: A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate that attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.