Abstract: Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal.

Abstract: A number of memory array units are placed on a die. Each memory array within a unit is coupled to a channel that includes one or more data lines coupled to a pad on the die. Each memory array unit utilizes a different channel. Memory array units are grouped together in pairs on the die to form memory array groups. The two channels of each memory array group form boundaries on the die. The pads coupled to each channel of a memory array group are positioned within those boundaries. The pads may be arranged such that the same pad layout can be used across different dies fabricated for use at different bus widths. In one embodiment, a set of the pads are used in applications where the die is configured for a first bus width and a portion of the pads used in the first bus width applications are not used in applications where the die is configured to for a second bus width.

Abstract: An integrated circuit memory device includes a memory, a read control circuit operatively associated with the memory and configured to produce data from the memory responsive to an externally-applied input clock signal, and an output latch configured to transfer data at an input thereof to an output pad of the memory device responsive to an externally-applied output clock signal. The device further includes a clock domain alignment circuit configured to receive the data produced by the memory and to responsively provide the data at the input of the output latch based on relative timing of the input clock signal and the output clock signal.

Abstract: A CAM array block is configured to perform a search operation in a staged segment-to-segment manner using a plurality of hybrid comparands that are pipelined into the CAM array block during consecutive stages of the search operation. These hybrid comparands include at least a virtual sector field and a data field. The CAM array block is also responsive to a segment address, which identifies an active segment of CAM cells in said CAM array block. The CAM array block may include a CAM array and a global mask cell sub-array that is electrically coupled to the CAM array. This global mask cell sub-array may be responsive to the segment address and a mode select signal. A bit/data line control circuit is also provided. The bit/data line control circuit is electrically coupled to the CAM array by bit lines and data lines and has inputs that are responsive to signals generated by the global mask cell sub-array. The device may also include an address translation unit that is responsive to an input address.

Abstract: Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop containing differential amplifiers that set the resolution limit of the output driver circuit. These output driver circuits include a first PMOS pull-up transistor having source and drain terminals electrically connected in series in a pull-up path of the output driver circuit. An NMOS pass transistor has a first current carrying terminal electrically connected to a gate terminal of the first PMOS pull-up transistor and a second current carrying terminal configured to receive a P-type analog reference voltage (VP). This P-type reference voltage controls the conductivity of the first PMOS pull-up transistor in the pull-up path. A gate terminal of the NMOS pass transistor is responsive to a pull-up data input signal (DINP).

Abstract: CAM devices include a segmented CAM array that is configured to support a long word search operation (e.g., x8N search) as a plurality of overlapping segment-to-segment search operations that are each performed across different rows within a group of rows in the CAM array and staggered in time relative to one another. To provide enhanced soft error immunity, these CAM devices may also include a CAM array having a row of lateral XY TCAM cells therein that are arranged in a repeating low-even, low-odd, high-even, high-odd sequence, where “low” and “high” represent the first and second halves of a CAM entry. Methods of operating a CAM device may include staggering the timing of overlapping segment-to-segment search operations across different rows within a CAM array using force-to-miss control signals to establish miss conditions on match lines of rows that are not to participate in a respective ones of the segment-to-segment search operations.

Abstract: Segmented CAM arrays are provided with dual-capture match line signal repeaters that support high speed pipelined search operations. A dual-capture match line signal repeater may extend between xR and xS segments of CAM cells within a respective row. This repeater provides high speed operation by quickly accessing the state (match or miss) of a match line segment when a corresponding segment of CAM cells connected to the match line segment undergo a respective stage of a pipelined search operation. If the match line segment is initially assessed as having a match signal thereon, then that match signal is passed to a next higher match line segment within the same row and a next stage search operation is commenced.

Abstract: A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource.

Abstract: Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period.

Abstract: An apparatus and method determine byte gain and loss adjustments that compensate for frequency differences between ingress and egress data rate signals in a SONET/SDH NE. The count of ingress data rate signal pulses at the time that data is requested by a switch fabric is compared to the count of egress data rate signal pulses at the time the requested data is passed through the switch fabric. If a delta phase equal to the difference in counts less a reference phase, is continuously greater than a positive value threshold for at least a time threshold period, then a byte gain adjustment is determined. On the other hand, if the delta phase is continuously less than a negative value threshold for at least the time threshold period, then a byte loss adjustment is determined.

Abstract: Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g.

Abstract: Asynchronous memory devices utilize loopback circuitry to provide efficient and high speed “flow-through” of write data when conventional flow-through operations are not available. An exemplary memory device includes a memory array having first and second ports that can each support asynchronous read and write access and a first input/output control circuit. The first input/output control circuit is electrically coupled to the first port and includes a first sense amplifier, which is configured to receive read data from the first port, and a first bypass latch having an output coupled to the first sense amplifier. A second input/output control circuit is also provided. The second input/output control circuit is electrically coupled to the second port and includes a second sense amplifier, which is configured to receive read data from the second port, and a second bypass latch.

Abstract: A grid array microelectronic package includes a substrate and an array of external connectors on the substrate that are arranged in rows and columns to define a periphery of the array and the interior of the array. A routing channel is provided in the array that increases the periphery of the array by at least four external connectors, compared to absence of the routing channel. The routing channel may be made of two missing external connectors, at least two strapped external connectors and/or at least two “no-connect” external connectors in the array that extend from the periphery of the array towards the interior of the array. Signal conductors may extend along the routing channel.

Abstract: Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log2N stages of 2-to-1 multiple match gates, where N=2k and k is a positive integer.

Abstract: A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate. The doped layer and well region are maintained at a voltage potential that is between a threshold voltage and a breakdown voltage defined the PN junction formed at their interface. The resulting structure attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.

Abstract: Flip-flop devices provide fast clock-to-Q timing that exploits the pulsed nature of outputs generated by a clocked sense amplifier. These flip-flop devices include an output stage, which has a PMOS pull-up transistor and an NMOS pull-down transistor therein, and a clocked sense amplifier at an input stage. The clocked sense amplifier is configured to generate first and second data output signals (/SET and /RESET). These data output signals are provided to a signal edge acceleration stage. This signal edge acceleration stage is configured to generate the pull-up and pull-down control pulses in response to the first and second data output signals, respectively. This leading edge acceleration stage includes a pull-up buffer having an odd (even) number of inverters therein that are skewed to accelerate the leading edge of the pull-up control pulse relative to a trailing edge of the pull-up control pulse.

Abstract: A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.

Abstract: A method for generating a photoresist structure is disclosed in which a layer of photoresist is deposited over a semiconductor substrate. In a first exposure, the layer of photoresist is exposed to deep ultraviolet light. A second exposure is then performed using a different wavelength of light to pattern the layer of photoresist. The photoresist is then developed so as to form a photoresist structure having reduced thickness and rounded corners. This gives a photoresist structure having a reduced shadow area. An angled ion implant can then be performed using the photoresist structure as a mask.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: Ternary CAM cells are provided that have extremely small layout footprint size and efficient layout aspect ratios that enhance scalability. The cells also have high degrees of symmetry that facilitate high yield interconnections to bit, data and match lines. A 16T ternary CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the cell. First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.