Patents Assigned to Integrated Device Technology
-
Patent number: 6232647Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.Type: GrantFiled: November 5, 1999Date of Patent: May 15, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Shih-Ked Lee, Chu-Tsao Yen
-
Patent number: 6230249Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.Type: GrantFiled: August 7, 1998Date of Patent: May 8, 2001Assignee: Integrated Device Technology, Inc.Inventors: Raymond K. Chan, Mario F. Au
-
Patent number: 6226756Abstract: The present invention provides an interface for exchanging clocking signals and other information between a computer subsystem based on a first clocking scheme of a first processor and a second processor. The second processor and computer subsystem are coupled to the interface. The interface may be included on a circuit card that is removably coupled to the computer subsystem. The interface includes an emulator for emulating the first clocking scheme thereby enabling the second processor to function with the computer subsystem.Type: GrantFiled: November 3, 1998Date of Patent: May 1, 2001Assignee: Integrated Device Technology, Inc.Inventor: Martin Mueller
-
Patent number: 6222212Abstract: An integrated circuit structure is described which includes a base semiconductor structure and a programmable semiconductor structure which are fabricated separately and later joined to form the integrated circuit structure. The base semiconductor structure includes conventional semiconductor devices fabricated in accordance with a first set of design rules. The programmable semiconductor structure includes programmable elements fabricated in accordance with a second set of design rules which may be different than the first set of design rules. The programmable elements are used to control the configuration of the integrated circuit structure or to provide field programmable devices for use in the integrated circuit structure.Type: GrantFiled: March 25, 1996Date of Patent: April 24, 2001Assignee: Integrated Device Technology, Inc.Inventors: Ji-Min Lee, Joseph F. Santandrea, Chuen-Der Lien, Anita Hansen, Leonard Perham
-
Patent number: 6215708Abstract: A memory circuit that operates in response to a VCC supply voltage and a ground voltage is provided. The memory circuit includes a word line voltage generation circuit that generates a fixed word line voltage. The fixed word line voltage is selectively applied to word lines of the memory circuit. The word line voltage generation circuit generates the fixed word line voltage for all values of the VCC supply voltage between the minimum VCC supply voltage and the maximum VCC supply voltage. The fixed word line voltage is referenced to the ground voltage, rather than the VCC supply voltage. Because the ground voltage does not vary, the boosted word line voltage of the present invention can be controlled more precisely than prior art boosted word line voltages, which are referenced to the VCC supply voltage. This improved control enables the boosted word line voltage to be fixed for the entire range of the VCC supply voltage.Type: GrantFiled: September 30, 1998Date of Patent: April 10, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Chau-Chin Wu
-
Patent number: 6215350Abstract: A fast switching, device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.Type: GrantFiled: October 24, 1997Date of Patent: April 10, 2001Assignee: Integrated Device Technology, Inc.Inventor: David C. Wyland
-
Patent number: 6216205Abstract: Methods of controlling memory buffers having tri-port cache arrays therein include the steps of reading data from a current read register in the cache memory array to an external peripheral device, and writing data from an external peripheral device to a current write register in the cache memory array. Tri-port controller logic and steering circuitry are also preferably provided for performing efficient read and write arbitration operations to make next-to-read and next-to-write registers always available in the cache memory array. The use of four separate registers in the cache memory array, efficient steering circuitry and the tri-port controller logic essentially eliminates the possibility that gaps or stoppages will occur in the flow of data into and out of the buffer memory device during read and write operations.Type: GrantFiled: May 21, 1998Date of Patent: April 10, 2001Assignee: Integrated Device Technology, Inc.Inventors: Bruce Lorenz Chin, Robert J. Proebsting
-
Patent number: 6216239Abstract: A method and structure for identifying disturbed memory cells within a memory cell array are provided. A test circuit consists of several cells within the memory cell array, and are coupled to the cells in the memory cell array. The test cells are also coupled to a test cell word line. During a long-write test, all word lines within the memory cell array are first deselected. The test cell word line is then selected, which causes the test cells to provide a logic high or a logic low voltage to the bit lines within the memory cell array. The voltage provided to the bit lines can be used to write test data into the memory cells or to create a write-disturb mode. The test cells can be either memory cells similar to that used in the memory cell array, or a circuit that couples a voltage source to the bit lines when activated.Type: GrantFiled: September 15, 1997Date of Patent: April 10, 2001Assignee: Integrated Device Technology, Inc.Inventor: Chuen-Der Lien
-
Patent number: 6212109Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. In an exemplary embodiment during an internal write operation, write circuitry supplies a small differential voltage to the selected bit line sense amplifiers, which “swallows” the normal read signal, before bit line sensing. The bit line sense amplifiers then “write” the level into the memory cell during normal latching. This provides for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by letting a selected bit line sense amplifier restore the voltage levels onto the selected bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell.Type: GrantFiled: August 11, 1999Date of Patent: April 3, 2001Assignee: Integrated Device Technology, Inc.Inventor: Robert J. Proebsting
-
Patent number: 6212607Abstract: A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R).Type: GrantFiled: January 17, 1997Date of Patent: April 3, 2001Assignee: Integrated Device Technology, Inc.Inventors: Michael Miller, John Mick, Jeff Smith, Mark Baumann, Chris Schott
-
Patent number: 6208195Abstract: An integrated circuit fast transmission switching device is provided which comprises a first input/output lead having a bus capacitance Cb; a second input/output lead having a bus capacitance Cb; a first bidirectional field-effect transistor having an internal resistance Ri and an internal capacitance Ci including a first input/output terminal and a second input/output terminal and a gate terminal, said first terminal being connected to said first lead and said second terminal being connected to said second lead, so as to pass bidirectional external data signals between said first and second leads when said transistor is turned on and so as to block the passage of external data signals between said first and second leads when said transistor is turned off; wherein Ri and Ci for the field-effect transistor are such that Ri(Ci+Cb) is less than 6.Type: GrantFiled: September 19, 1997Date of Patent: March 27, 2001Assignee: Integrated Device Technology, Inc.Inventor: David C. Wyland
-
Patent number: 6204557Abstract: An integrated circuit structure that includes a patterned uppermost conductive layer having a current-carrying trace. The current-carrying trace is connected to an underlying substrate by a multi-layer interconnect structure. The current-carrying trace, which is located around the outer edges of the integrated circuit structure, has at least one edge exhibiting a serpentine pattern. A topside film is located over the patterned uppermost conductive layer, wherein the topside film exhibits an increased thickness adjacent to the serpentine pattern. The increased thickness of the serpentine pattern results in a relatively strong topside film structure near the edges of the substrate. As a result, the portions of the topside film located over inner traces of the uppermost conductive layer are protected from excessive forces during thermal cycling.Type: GrantFiled: September 13, 1999Date of Patent: March 20, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Chun-Ya Chen, Pauli Hsueh, Ta-Ke Tien, Leonard Perham
-
Patent number: 6205049Abstract: A static random access memory (SRAM) system that includes a five-transistor SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the VCC supply voltage if the SRAM cell is not being written (i.e., during a read mode or a standby mode). If the SRAM cell is being written, the cell voltage control circuit supplies the SRAM cell with a cell voltage that is less than the VCC supply voltage. The lower cell voltage weakens pull-down transistors in the SRAM cell, thereby enabling logic high values to be written to the SRAM cell. In one embodiment, the cell voltage is less than the VCC supply voltage minus the threshold voltage of an access transistor of the SRAM cell. The cell voltage is high enough to enable the SRAM cell to reliably store data during a write disturb condition.Type: GrantFiled: August 26, 1999Date of Patent: March 20, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Chau Chin Wu
-
Patent number: 6198682Abstract: A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared between two pairs of bit lines. Half of the bit line pairs within each array block are served by a sense amplifier located above the array block, and the remaining half are served by a sense amplifier located below the array block. A read amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a bus line before bit line sensing has occurred. This read amplifier may be connected to the bit lines, the internal sense amplifier nodes, a local I/O line, or a local output line. In a preferred embodiment, a second stage amplifier further buffers the signal and drives a pair of global output lines which extend the full height of the memory bank to respective I/O circuits.Type: GrantFiled: June 10, 1999Date of Patent: March 6, 2001Assignee: Integrated Device Technology, Inc.Inventor: Robert J. Proebsting
-
Patent number: 6194296Abstract: Planarized polycide structures and methods for making the same. One embodiment includes a semiconductor structure having an irregular upper surface caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of polysilicon is located over the irregular upper surface of the semiconductor structure. The polysilicon layer has a substantially flat upper surface. A metal silicide layer is located over the flat upper surface of the polysilicon layer to form a polycide structure. This planarized polycide structure can be used, for example, as a gate electrode in an FET. In another embodiment, the planarized polycide structure includes a first polysilicon layer located over a semiconductor substrate. The polysilicon layer has an irregular upper surface.Type: GrantFiled: October 31, 1995Date of Patent: February 27, 2001Assignee: Integrated Device Technology, Inc.Inventor: Chuen-Der Lien
-
Patent number: 6191460Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.Type: GrantFiled: September 7, 1999Date of Patent: February 20, 2001Assignee: Integrated Device Technology, Inc.Inventors: Jeong Y. Choi, Chuen-Der Lien
-
Patent number: 6183940Abstract: A method of retaining the integrity of a photoresist pattern is provided where the patterned photoresist is treated prior to etching the principle layer. The pre-etch treatment encompasses a plasma treatment. In some embodiments employing an anti-reflective coating (ARC) layer, an isolation/protective layer is used to isolate the ARC from the photoresist. In some embodiments, the pre-etch treatment, advantageously provides for patterning the isolation/protection layer.Type: GrantFiled: March 17, 1998Date of Patent: February 6, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chen-Yu Wang, Tseng You Syau, Ching-Kai Lin
-
Patent number: 6173425Abstract: Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e.g., address) of a current write register (receiving test data) may be “tagged” to a series of test words written into the current write register during test mode operation.Type: GrantFiled: April 15, 1998Date of Patent: January 9, 2001Assignee: Integrated Device Technology, Inc.Inventors: Roland T. Knaack, Bruce Lorenz Chin
-
Patent number: 6165918Abstract: Systems and methods are described for fabricating semiconductor gate oxides of different thicknesses. Two methods for forming gate oxides of different thicknesses in conjunction with local oxidation of silicon (LOCOS) are disclosed. Similarly, two methods for forming gate oxides of different thicknesses in conjunction with shallow trench isolation (STI) are disclosed. Techniques that use two poly-silicon sub-layers of substantially equal thickness and techniques that use two poly-silicon sub-layers of substantially unequal thickness are described for both LOCOS and STI. The systems and methods provide advantages because gate uniformity and quality are improved, the processes and resulting devices are cleaner, and there is less degradation of carrier mobility.Type: GrantFiled: May 6, 1999Date of Patent: December 26, 2000Assignee: Integrated Device Technology, Inc.Inventors: James Yingbo Jia, Jeong-Yeol Choi
-
Patent number: 6166334Abstract: Apertures in a tape formed on a substrate allow straight plating of solder bumps to heights above 4 mils. The solder bumps are combined with a lower density material to form an hourglass-shaped structure which allows interconnections to bonding pads of electronic components with pitches less than 9 mils.Type: GrantFiled: April 6, 1999Date of Patent: December 26, 2000Assignee: Integrated Device Technology, Inc.Inventor: Terry R. Galloway