Abstract: An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of multiplication techniques, such as bit-pair recoding or the Booth algorithm, to perform multiplication and negate multiplication operations. The multiplier circuit uses an encoder circuit to produce encoded multiplier strings in accordance with such multiplication techniques. The multiplier circuit reorders bits of such encoded multiplier strings to cause a binary multiplier circuit to generate the negate product -B*C rather than the product B*C. The reordering can be accomplished in any manner, such as by a bus coupling the encoder circuit to the binary multiplier circuit. The encoder circuit can be coupled to the binary multiplier circuit using two buses and a multiplexor circuit.

Abstract: A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.

Abstract: A method for distributing the available bit rates in a variable bit rate service under asynchronous transfer mode is provided by distributing the available bit rates in logarithmic-linear steps, so that the ratio between two successive available bit rates are substantially constant. To minimize computation required to calculate the next available allowable cell rate, a table look-up method can be used in conjunction with a state machine. In one embodiment, the table look-up operation includes accessing a rate increase table and a rate decrease table. A selection circuit is provided to choose the next allowable cell rate from the current cell rate, and the output values obtained from looking up the rate increase table and the rate decrease table.

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup transistor and a pulldown transistor. The two pullup and pull down transistors are coupled in series between two drive transistor circuits. In one aspect of the invention, the pullup and pulldown drive transistor circuits provide momentary low impedance connection of the pullup and pulldown transistors to the respective pullup and pulldown voltage sources during the initial switching waveforms of the digital signal. After the initial switching of the digital signal, the pullup and pulldown drive transistor circuits provide precise V.sub.OH and V.sub.OL voltage output levels and provide high impedance filtering of voltage supply line and ground line noise.

Abstract: A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V.sub.CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the V.sub.CC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the V.sub.CC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the V.sub.CC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match sense line prior to a compare operation.

Abstract: A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.

Abstract: An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i.e., burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: The function selection signal of an ALU is resistively decoupled or serially coupled to the input multiplexers of the ALU. By producing delayed function selection signals and decoupling the delayed function signals from the input multiplexers, the input multiplexers are serially activated. This need not impact the overall speed of the ALUs, since the adders are also serially activated by virtue of the carry signal ripple. However, by resistively decoupling the function selection signal from the input multiplexers, the load seen by the input driver that drives the function selection signal inputs of the multiplexer may be reduced, thereby allowing the least significant bit input multiplexer to be activated more rapidly. Moreover, resistive decoupling may be implemented by polysilicon resistors, thereby allowing metal interconnect layers in the integrated circuit to be used for other purposes.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay.

Abstract: An integrated circuit package includes a number of electrical conductors that are completely or at least partially surrounded by a gas instead of a solid material (having no cavities) used in the prior art. Such use of a gas reduces the dielectric constant in a region around each of the electrical conductors, as compared to the dielectric constant of a solid dielectric material. In one implementation, a number of leads are kept separated from a substrate by a number of electrically conductive support members attached to the substrate. Each lead is electrically coupled (e.g. by a bond wire) to a die pad on a die that is supported by the package in the normal manner. The leads are initially formed as portions of a lead frame (e.g. by etching or stamping), and are held separate from each other by the respective support members. The support members are electrically coupled (e.g. by traces and vias in the substrate) to terminals (e.g. pins, balls or lands) of the package.

Abstract: A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R).

Abstract: The reliability of an antifuse can be increased and/or the thickness of the antifuse dielectric can be decreased by the use of a rapid thermal nitridation nitride layer as part of the antifuse dielectric. The RTN nitride layer is denser and has fewer pinholes than nitride layers formed by chemical vapor deposition. The rapid thermal nitridation also produces a good contact with a bottom electrode containing silicon as well as providing a nucleation layer for any additional nitride layer formed by chemical vapor deposition. Increasing the reliability of the antifuse dielectric allows it to be thinner, and thus allows for the programming of the dielectric layer at lower programming voltages.

Abstract: An input buffer for use in an integrated circuit having a V.sub.CC voltage supply and a V.sub.SS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the V.sub.CC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the V.sub.SS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the V.sub.CC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: An exemplary 18 MBit memory array includes four banks of array blocks. At the end of an active cycle, the exemplary memory array is automatically taken back into precharge without waiting for a control signal. One edge of a clock causes the memory array to execute a useful cycle, then to automatically reset itself in preparation for a new cycle, preferably using two sets of precharge signals- one is an automatically timed pulse, while the other stays on until the start of the next cycle. Both turn on automatically at the same time just after the selected word line is brought low. One equilibrate signal is turned off by a timed pulse just when the bit line equilibration is substantially complete (i.e., at the end of the active cycle), while the other equilibrate signal is turned off by the start of the subsequent cycle. The pulsed equilibrate signal drives much larger internal capacitive loads, such as large equilibration devices, while the non-pulsed (i.e.

Abstract: Method, apparatus and computer program products for transforming from model to screen coordinates by assigning specified subsets of the plurality of parallel processing elements respective model space geometric primitives. The respective specified subsets of the plurality of parallel processing elements are then provided a plurality of transformation matrices associated with respective model space geometric primitives. A unified transformation matrix for each primitive is then produced from the plurality of transformation matrices associated with each particular model space geometric primitive. The resulting unified transformation matrices are then applied to said geometric primitives by the processing elements to translate the geometric primitive from model coordinates to screen coordinates.

Abstract: A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled inverters and a pair of access transistors. The SRAM cell stores a data value at the output node of one of the inverters and an inverse data value at the output node of the other one of the inverters. An access transistor is connected between each output node and a match line. The match line is connected across the access transistors such that the match line is coupled to the output nodes of the inverters when the access transistors are turned on. Data lines are connected to the gates of the access transistors, and are coupled to receive a data value and an inverse data value. The 6-T CAM cell of this embodiment can be coupled to a plurality of identical 6-T CAM cells to form an array. Each row of CAM cells is coupled to the same match line.

Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).