Abstract: Voltage dividing resistors (R1a, R1b, R2a, R2b) are connected in parallel with diode connected bipolar transistors (Q1, Q2) for splitting the voltage to the inputs of an operational amplifier (62, 82). Current is provided to this arrangement by current sources (I1, I2). When the supply voltage is about 0.85 volts, a temperature insensitive reference voltage of about 200 millivolts is available at the drain of a second transistor (M2, M2).

Abstract: A die paddle for receiving an integrated circuit die in a plastic substrate. The die paddle is defined by a copper film on the plastic substrate and comprises a plurality of via holes through the plastic substrate, a plurality of opening through the copper film, and a gold-containing ring formed on the peripheral portion of the copper film. The outermost openings (and/or the outermost via holes) and the gold-containing ring are separated by a distance of about 1 to about 20 mils.

Abstract: A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

Abstract: A transmission mode detector for digital receiver is proposed. The transmission mode detector comprises a RF tuner for receiving RF signals and generating intermediate frequency (IF) signals. An envelope detector is employed to filter the IF signals and generate rough envelope signal and a hard-decision machine is employed to quantize the rough envelope signal into hard-decision binary signals. The transmission mode detector further comprises a glitch remover to remove the unwanted glitch in the binary signals and generate envelope signal. An A/D converter is used to quantize the IF signals and generate digital signal. Further more, an I/Q de-multiplexer is used to extract the in-phase and the quadrature terms of the OFDM symbol from the digital signal. The transmission mode detector then detects the transmission mode by a mode detect unit according to the period of the envelope signal.

Abstract: A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the circuit board substrate, forming a solder mask over the circuit board substrate and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A fast line drawing method. First, the coordinates of two end points are received and a current point is assigned to one of the end points. The differences of x and y coordinates (?x and ?y) and the sum of error E are computed, the integer part of ?x over ?y is denoted as Q. The current point is checked to determine whether it has reached the end point. If not and the value of E is negative, a point at the current point is drawn. The y-coordinate of the current point and E are updated by (Y+1) and (E?2?x) respectively if E is non-negative, a span of pixels from (X,Y) to (X+Q?1,Y) are drawn if the coordinate of last of Q points is less than the end point. Otherwise, a span of pixels from (X,Y) to (x2,Y) are drawn.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: A radiation detection apparatus is capable of detecting and locating events, such as a fire or the appearance of an intruder, in a scene under surveillance. The apparatus comprises an array of detector elements, e.g. infrared detectors. The apparatus has two fields of view, namely a first field of view defined by a lens providing a single focussed image of a distant scene on the array and a second field of view defined by a reflector arranged between a plane of the array and a plane of the lens whereby to reflect onto the detector array radiation entering the lens from outside the first field of view. One or more processors are provided to distinguish events in the second field of view from those in the first field of view.

Abstract: A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Abstract: A method and system for estimating camera motion parameters and determining a filter to correct for camera motion errors. The estimating method and system includes obtaining an observation point set including a plurality of observed point vectors, computing a plurality of motion output vectors by performing a recursive least squares (RLS) process based on a plurality of motion parameter vectors, and comparing the plurality of motion output vectors to the plurality of observed point vectors. The filter determining method and system includes determining a plurality of desired motion point vectors, computing a plurality of estimated motion point vectors by means of an RLS algorithm, and computing the filter based on a difference between the plurality of estimated motion point vectors and the plurality of desired motion point vectors.

Abstract: An apparatus and a method for supporting coexistence of an external AGP graphics adapter with an embedded graphics adapter. The embedded graphics adapter may be regarded as a PCI device, and the graphics memory of embedded graphics adapter is integrated into DRAM of a computer system. The corelogic and software capable of graphics address remapping and directed accessing graphics memory of the embedded graphics adapter for supporting external AGP graphics adapter and embedded graphics adapter respectively. The embedded graphics adapter could be an AGP device while the external graphics adapter would be a PCI device, and vice versa.

Abstract: A circuit for increasing the voltage/current level of a signal to drive a power transistor from a low voltage input. The gate drive circuit comprises a voltage multiplier for increasing the voltage level of a low voltage input signal, a level shifter for shifting the voltage level of a logic signal to a level relative to a voltage signal produced by the voltage multiplier, and a source follower, connected to the level shifter, for increasing the current of the increased voltage, level shifted output signal of the level shifter. The resulting multiplied, shifted, and increased current signal can be used to drive a power transistor.

Abstract: A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Abstract: A flame detection apparatus has a focused array based sensor which is responsive to radiation having a predefined wavelength for generating an image of the infrared radiation emitted within a monitored region, and means for measuring the spectral ratio of the intensity of radiation having a first wavelength emitted within the monitored region to the intensity of radiation having a second wavelength emitted within the monitored region. Processing means analyzes the output of the focused array based sensor and the spectral ratio measuring means for responses indicative of the presence of a flame within the monitored region.

Abstract: A process via mismatch detecting device is disclosed. Because the vias in the detecting circuit of process via mismatch detecting device are mismatched while the vias between the metal layers of the chips are mismatched, by appropriately placing vias in detecting circuit of process via mismatch detecting device properly, metal lines of different metal layers in the detecting circuit can become short-circuited by mismatched vias, so as to output a voltage signal that is higher after vias mismatch and is regarded as the result of detecting via mismatch. Therefore, the direction and quantity of via mismatch between the metal layers in the chip are detected and monitored effectively, so as to optimize the process. Thus, the yield of process is increased and the cost is decreased.

Abstract: A two dimensional array of resistive bolometers (B) is arranged in rows and columns. Amplifiers (A0, A1 etc) amplify signals obtained from the bolometers. Instead of providing one amplifier per column, a smaller number of amplifiers is used each of which is connected to a plurality of column sense lines (L) via a multiplexer (M0, M1 etc).

Abstract: Architecture of an efficient adaptive digital echo canceller includes a frequency domain update block, a far-end signal estimation block and a time domain echo cancellation block. The echo canceller has a training mode in which the frequency domain update block and far-end signal estimation block are first trained to estimate the echo channel and target channel. After the training mode, the time domain echo cancellation block uses the estimated echo channel to synthesize an echo replica and subtracted it from the received signal continuously before or in an operation mode. When a synchronization frame is received in the operation mode, the frequency domain update block and the far-end signal estimation block are used to retune both echo channel and target channel for improving system performance.