Patents Assigned to Integrated Systems
  • Publication number: 20020124520
    Abstract: The present invention comprises a moment resisting connection that comprises a column connection, a girder connection, and a field weld that couples the column connection to the girder connection. The column connection includes a column and a pair of column side plates in which each column side plate is coupled to the flanges of the column. The girder connection comprises a girder and a pair of girder side plates in which each girder side plate is operatively coupled to a doubler plate that is coupled to each girder flange. Alternatively, each girder side plate is joined to each girder flange. The field weld is performed by positioning the girder connection so that it may be welded to the column connection. The present invention also teaches a method comprising the steps of welding each column side plate to the flanges of the column. Additionally, the steps of fixedly coupling each girder side plate to the flanges of the girder is described.
    Type: Application
    Filed: February 8, 2002
    Publication date: September 12, 2002
    Applicant: Arcmatic Integrated Systems, Inc.
    Inventors: Charles A. Bock, Willaim L. Bong
  • Patent number: 6448966
    Abstract: The present invention discloses a method for improving 3D computer graphics by pre-sorting display lists or display primitives. The display lists or display primitives with smaller indicators are placed at the front end of a reordered region, and the display lists or display primitives with larger indicators are placed at the rear end of the reordered region. The indicators are the minimum, average or maximum values computed with the depth values, or even be the depth values by themselves. After a sorting action is finished, the method of the present invention will enter a Z-buffer pre-test process. Because the display lists or display primitives have been sorted from the lowest to the largest depth valves, the probability of skipping hidden pixels in the Z-buffer pre-test process will be increased and the unnecessary computations of hidden pixels will be reduced in the rendering process.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: September 10, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventor: Kwo-Woei Yet
  • Patent number: 6448967
    Abstract: Memory bandwidth is the bottleneck in a three-dimensional display system. A method with Z-Buffer pre-test reduces the memory accesses in the three-dimensional graphics system. This method includes two depth(Z) caches, a control logic for controlling memory access and two Z(depth) cache mechanisms. If the incoming pixel with Z-Buffer pre-test fails, then the pixel is discarded. Thus, the following texture mapping and other tests for the pixel are eliminated and memory accesses are reduced.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 10, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventor: Chien-Chung Hsiao
  • Patent number: 6444034
    Abstract: An apparatus for preventing electrostatic destruction of integrated circuits coats an electrostatic agent on surfaces of the integrated circuits to avoid accumulation of static electricity caused by dynamic contact friction. The apparatus comprises a belt, at least one motor, at least one spray nozzle, at least one dispenser or controller and at least one photo switch. The integrated circuits are placed on the belt. The motor drives the belt and therefore the integrated circuits step by step to the spray nozzle to coat the electrostatic agent on the surfaces of the integrated circuits. The controller controls the output rate of the electrostatic agent from the spray nozzle. The photo switch is connected to the spray nozzle and dispenser to detect the integrated circuits as they pass the spray nozzle.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: September 3, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Yi-Chang Hsieh, Lai-Fue Hsieh, Mu-Sheng Liao, Ching-Jung Huang
  • Patent number: 6437611
    Abstract: The present invention discloses an output driver circuit providing linear I/V characteristics, i.e. constant output impedance, during output voltage transitions. The output driver circuit includes a first input transistor, a second input transistor, a first pair of transistors, a second pair of transistors, a first output transistor and a second output transistor. The first input transistor inputs a first input signal and has an output node coupled to the output node of the output driver circuit. The second input transistor inputs a second input signal and has an output node coupled to the output node of the output driver circuit. The first pair of transistors is responsive to a first control signal and the output signal for generating a second control signal. The second pair of transistors is responsive to a third control signal and the output signal for generating a fourth control signal.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: August 20, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Shun-Yuan Hsiao, Chun-Ming Leu
  • Publication number: 20020109096
    Abstract: A flame detection apparatus has a focused array based sensor which is responsive to radiation having a predefined wavelength for generating an image of the infrared radiation emitted within a monitored region, and means for measuring the spectral ratio of the intensity of radiation having a first wavelength emitted within the monitored region to the intensity of radiation having a second wavelength emitted within the monitored region. Processing means analyses the output of the focused array based sensor and the spectral ration measuring means for responses indicative of the presence of a flame within the monitored region.
    Type: Application
    Filed: February 8, 2002
    Publication date: August 15, 2002
    Applicant: Infrared Integrated Systems Ltd.
    Inventor: Christopher Frederick Carter
  • Publication number: 20020101428
    Abstract: The invention provides a graphic engine and a method that reduces the idle time of the graphic engine by validity test. The validity test is performed when the back buffer is full and the graphic engine continues to write a primitive into a front buffer. The validity test compares the maximum Y-coordinate of the primitive with the Y-coordinate of the current scan line. If the maximum Y-coordinate of the primitive is less than the Y-coordinate of the current scan line, the graphic engine keeps on executing the primitive processing procedure. On the other hand, if the maximum Y-coordinate of the primitive is greater than or equal to the Y-coordinate of the current scan line, the graphic engine halts the primitive processing procedure until the maximum Y-coordinate of the primitive is less than the Y-coordinate of the current scan line.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 1, 2002
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Chien-chung Hsiao, Kwo-woei Yet, Chung-yung Lee
  • Publication number: 20020101420
    Abstract: A triangle shading method for a 3D graphic system includes the steps of (1) defining a starting position and two adjacent edges; (2) setting the tile containing the starting position as a target tile, then defining a target tile row; (3) checking if the lower boundary or upper boundary of the target tile crosses with the adjacent edges and pushing the address of crossing points into a stack if there exists such crossing points; (4) storing the associated data of the pixels of the target tile in memory; (5) checking if the target tile is the final tile of the target tile row, if not, setting the target tile to be the next tile of the current target tile and jumping to step (4); (6) checking if there are data remaining in the stack, if not, jumping to step (8); (7) popping a data from the stack, setting the data as a starting position and then jumping to step (2); (8) end.
    Type: Application
    Filed: January 25, 2002
    Publication date: August 1, 2002
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Hung-Ta Pai, Ming-Tsan Kao
  • Patent number: 6422718
    Abstract: A light source system in which light scattered inside a chamber (2) exits from a hole (3) to provide a light output from the system. The interior wall of the chamber (2) consists of a material which is very efficient at scattering incident light. Light emitted from a light source (1) undergoes at least one scattering event within the chamber (2) before escaping from the chamber (2) through the exit hole (3). Any geometrical attributes of the light from the source (1) are removed before the light exists from the chamber (2). The exit hole (3) can have a tube inside (4) and/or outside (5) the chamber (2) for collimating the light output. A mechanical shutter (7, 8) can be used as a simple dimmer mechanism for the light output from the system. The light source (1) can be positioned inside or outside the chamber (2).
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: July 23, 2002
    Assignee: Integrated Systems Technologies Limited
    Inventors: Keith Anderson, Geoffrey Archenhold, Kurt Baldwin, Andrew Neal
  • Patent number: 6423577
    Abstract: A method for reducing electrical noise inside a ball grid array package for installing capacitors between a plurality of power pads and ground pads on a top side of a substrate of the ball grid array package coats solder paste on the plurality of power pads and ground pads, coats adhesive glue beneath the plurality of capacitors, fixes the plurality of capacitors on the power pads and ground pads with the adhesive glue and solder paste, and solidifies the adhesive glue in a reflow soldering stove.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: July 23, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Cheng-Chung Cheng, Chen-Wen Tsai, Chia-Wen Shih
  • Patent number: 6424189
    Abstract: The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 23, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Jen-Pin Su, Tsan-Hui Chen, Wen-Hsiang Lin, Chun-Chieh Wu, Chang-Fu Lin
  • Publication number: 20020087653
    Abstract: The invention relates to a handheld portable card or disc (22) interface to a crash secure virtual hard disc (24) accessed through the card or disc with software storage capability, and a system (20) therefore. It virtually allows a user to log in on any computer (28) or terminal for retrieving own computer files from the hard disc (22) through the world wide web or Intranet and the like.
    Type: Application
    Filed: November 30, 2001
    Publication date: July 4, 2002
    Applicant: Creative Media Design at Integrated Systems Scandinavia Group AB
    Inventor: Dani Duroj
  • Patent number: 6412438
    Abstract: A remote plasma generator, coupling microwave frequency energy to a gas and delivering radicals to a downstream process chamber, includes several features which, in conjunction, enable highly efficient radical generation. In the illustrated embodiments, more efficient delivery of oxygen and fluorine radicals translates to more rapid photoresist etch or ash rates. A single-crystal, one-piece sapphire applicator and transport tube minimizes recombination of radicals in route to the process chamber and includes a bend to avoid direct line of sight from the glow discharge to the downstream process chamber. Microwave transparent cooling fluid within a cooling jacket around the applicator enables high power, high temperature plasma production. Additionally, dynamic impedance matching via a sliding short at the terminus of the microwave cavity reduces power loss through reflected energy. At the same time, a low profile microwave trap produces a more dense plasma to increase radical production.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: July 2, 2002
    Assignee: Matrix Integrated Systems, Inc.
    Inventors: Mohammad Kamarehi, Gerald M. Cox
  • Publication number: 20020079301
    Abstract: The present invention relates to a high deposition submerged arc welding system, comprising a gantry fixture, a weldhead, an operator control module and a modular control system. The gantry fixture is configured to receive a first plate and a second plate. The weldhead is operatively coupled to the gantry fixture and welds the first plate and second plate together with a metal powder, a welding wire and a flux. The operator control module is configured to receive a program for welding the first plate and the second plate together. The modular control system has a common bus which communicates the program to a plurality of control modules.
    Type: Application
    Filed: May 31, 2001
    Publication date: June 27, 2002
    Applicant: Arcmatic Integrated Systems, Inc.
    Inventors: William L. Bong, Charles Bock
  • Patent number: 6409932
    Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 25, 2002
    Assignee: Matrix Integrated Systems, Inc.
    Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
  • Patent number: 6409841
    Abstract: Disclosed are processes and systems for the production of useful organic product from diverse lignocellulose-containing biomass having increased yield and efficiency over existing processes. In particular, the present invention integrates dilute acid hydrolysis and alkaline delignification techniques in processes that enhance the efficiency and yiel of lignocellulostic biomass processing and enable the economic production lignin-based biodegradable plastics and other useful organic products.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: June 25, 2002
    Assignee: Waste Energy Integrated Systems, LLC.
    Inventor: Charles K. Lombard
  • Patent number: 6409129
    Abstract: A fixing device for setting anti-shock foot stand comprises a casing and a positioning seat, wherein a deck and a shed connected therewith are housed in the casing; an inner space is available in the shed; at least a slot is formed in a ceiling of the shed, and one end of the slot is extended to reach an edge of the ceiling; a plurality of tapped holes and through holes are disposed in the ceiling and in two lateral walls of the shed respectively; a plurality of through holes is arranged in the deck; and at least a tapped hole and a plurality of tapped holes are disposed in a ceiling and in two lateral walls of the positioning seat respectively at positions corresponding to those lateral through holes of the shed. When assembling, the foot stand is firstly placed in the slot, then the shed and the positioning seat are edge jointed together and locked with bolts.
    Type: Grant
    Filed: September 2, 2000
    Date of Patent: June 25, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Jun-Ming Chen, Chin-Jen Chen
  • Patent number: 6410386
    Abstract: A method for forming a metal capacitor in a damascene process is provided. Before the metal capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. The stacked layers are then subjected to a masking process and an etching process to form the thin-film capacitor and the metal wire with the remaining insulator and the remaining second metal layer thereon. The remaining second metal layer located on the metal wire is removed by another masking process and another etching process. After forming the capacitor and the metal wire, the upper interconnections are fabricated with Cu metal by damascene processes.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: June 25, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Chen-Chiu Hsue, Shyh-Dar Lee, Jen-Hann Tsai
  • Patent number: 6407630
    Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: June 18, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Chi-Tai Yao, Wei-Chen Shen, Hung-Chih Liu
  • Patent number: 6407595
    Abstract: A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: June 18, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Hung-Ju Huang, Hung-Ta Pai