Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack to have an improved ductility property.

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: In some embodiments, Cu—In—Ga precursor films are deposited by co-sputtering from multiple targets. Specifically, the co-sputtering method is used to form layers that include In. The co-sputtering reduces the tendency for the In component to agglomerate and results in smoother, more uniform films. In some embodiments, the Ga concentration in one or more target(s) is between about 25 atomic % and about 66 atomic %. The deposition may be performed in a batch or in-line deposition system. If an in-line deposition system is used, the movement of the substrates through the system may be continuous or may follow a “stop and soak” method of substrate transport.

Abstract: Methods and compositions for forming porous low refractive index coatings on substrates are provided. The method comprises coating a substrate with a sol-formulation comprising silica based nanoparticles and an alkyltrialkoxysilane based binder. Use of the alkyltrialkoxysilane based binder results in a porous low refractive index coating having bimodal pore distribution including mesopores formed from particle packing and micropores formed from the burning off of organics including the alkyl chain covalently bonded to the silicon. The mass ratio of binder to particles may vary from 0.1 to 20. Porous coatings formed according to the embodiments described herein demonstrate good optical properties (e.g. a low refractive index) while maintaining good mechanical durability due to the presence of a high amount of binder and a close pore structure.

Abstract: Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second res

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

Abstract: Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

Abstract: Multiple waste streams, including incompatible chemicals such as concentrated acids and/or strong base effluents, are handled together without the need for limiting or interrupting the processes run by the wafer processing tools. In some embodiments, waste tanks are primed with diluents, such as water, and a predetermined percentage of diluent is maintained in the waste tanks. In some embodiments, a diluent is flowed into the waste tanks concurrently with the waste pumping to generate a rinsing action for the waste tanks. Methods of the present disclosure accommodate both gravity type and vacuum type waste tanks.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. The current invention describes silicon texturing formulations that include at least one high boiling point additive. The high boiling point additive may be a derivative compound of propylene glycol or a derivative compound of ethylene glycol. Processes for texturing a crystalline silicon substrate using these formulations are also described. Additionally, a combinatorial method of optimizing the textured surface of a crystalline silicon substrate is described.