Abstract: Provided are voltage controlling assemblies that may be operable as clocks and/or oscillators. A voltage controlling assembly may include a comparator and a variable resistance device connected to one differential signal node of the comparator. The other node may be connected to a capacitor. Alternatively, no capacitors may be used in the assembly. During operation of the voltage controlling assembly, the variable resistance device changes its resistance between two different resistive states. The change from a low to a high resistive state may be associated with a voltage spike at the differential signal node of the comparator and trigger a response from the comparator. This resistance change may have a delay determining an operating frequency of the voltage controlling assembly. Specifically, the variable resistance device in the low resistive state may be kept for a period of time at a certain voltage before it switches into the high resistive state.

Abstract: Embodiments described herein provide systems and methods for performing vapor deposition processes on substrates. A housing defining a processing chamber is provided. A substrate support is positioned within the processing chamber and configured to support a substrate. A fluid supply system including a plurality precursor sources is included. A fluid conduit assembly is coupled to the fluid supply system and configurable to selectively expose a first site-isolated region defined on the substrate to the respective precursors of a first and a second of the plurality of precursor sources and selectively expose a second site-isolated region defined on the substrate to the respective precursors of a third and a fourth of the plurality of precursor sources.

Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract: Ternary metal nitride layers suitable for thin-film resistors are fabricated by forming constituent layers of complementary components (e.g., binary nitrides of the different metals, or a binary nitride of one metal and a metallic form of the other metal), then annealing the constituent layers to interdiffuse the materials, thus forming the ternary metal nitride. The constituent layers (e.g., 2-5 nm thick) may be sputtered from binary metal nitride targets, from metal targets in a nitrogen-containing ambient, or from metal targets in an inert ambient. Optionally, a nitrogen-containing ambient may also be used for the annealing. The annealing may be 10 seconds to 10 minutes at 500-1000° C. and may also process another component on the same substrate (e.g., activate a diode).

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. The gate dielectric layer includes titanium. An interface layer is formed above the gate dielectric layer. The interface layer includes silicon. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof The ReRAM cells may include a first layer operable as a bottom electrode. The ReRAM cells may also include a second layer operable as a variable resistance layer configured to switch between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have a substantially constant electrical resistivity. Moreover, the third layer may include a ternary metal-silicon nitride having a ratio of metal to silicon that is between about 1:1 and 1:4. Furthermore, the ternary metal-silicon nitride may include a metal that has an atomic weight that is greater than 90. The ReRAM cells may further include a fourth layer operable as a top electrode.

Abstract: Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blende crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. A contact layer is formed above the IGZO channel layer. The contact layer includes arsenic. A source electrode and a drain electrode are formed above the contact layer.

Abstract: X-ray fluorescence (XRF) monitoring of characteristic peaks while etching thin-film layers can reveal coverage defects and thickness nonuniformity in the top film. To measure coverage and uniformity while screening candidate layer materials and processes, the candidate layers may be formed above an underlayer of a different composition. A wet etchant that selectively etches the underlayer faster than the candidate layer is applied to the candidate layer, and the XRF spectrum is monitored. Pinholes, cracks, islands, and nonuniform thickness in the candidate layer produce characteristic features in the time-dependent behavior of XRF peaks from the underlayer and/or the candidate layer. “Etch/XRF” tests can be used to rapidly and objectively identify the most uniform contiguous candidate layers to advance to further screening or production. XRF may also be calibrated against a known thickness indicator to detect the approach of a desired endpoint in an etch process.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer formed on a substrate. The first layer may be operable as a bottom electrode. The ReRAM cells may also include a second layer formed over the first layer. The second layer may be operable as a variable resistance layer configured to switch reversibly between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have an electrical resistivity that is substantially constant. Moreover, the third layer may include a ternary metal carbide. The ReRAM cells may also include a fourth layer formed over the third layer. The fourth layer may be operable as a top electrode.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

Abstract: Provided are methods of high productivity combinatorial (HPC) screening of work function materials. Multiple test materials may be deposited as separate blanket layers on the same substrate while still forming individual interfaces with a common base layer. The thickness of each test material layer ensures that its work function properties are not impacted when other layers are deposited over that layer. A method may involve depositing a blocking layer over the base layer and selectively removing the blocking layer from a first site isolated region. A first test material is then deposited as a blanket layer and forms an interface with the base layer in that first region only. The first test material layer and the blocking layer are selectively removed from a second site isolated region followed by depositing a second test material layer as another blanket layer, which forms an interface with the base layer in the second region only.

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract: Provided are methods of forming nitrides at low substrate temperatures, such as less than 500° C. or even less than 400° C. The nitrides can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), and other like techniques. The low substrate temperatures allow using various temperature sensitive precursors, such as Tetrakis(DiMethylAmino)Hafnium (i.e., TDMAHf) or TertiaryButylimido-Tris(DiEthylamino)Tantalum (i.e., TBTDET), to form nitrides of components provided by these precursors. Furthermore, the low temperatures preserve other structures present on the substrate prior to forming the nitride layers. Nitrogen-containing precursors with low dissociation energy are used in these methods. Some examples of such nitrogen-containing precursors include hydrazine (N2H4), diazene (N2H2), triazene (N3H3), triazane (N3H5), alkyl-substituted variations thereof, and salts thereof. Also provided are methods of forming oxy-nitrides using low substrate temperatures.

Abstract: Embodiments described herein provide methods and systems for evaluating indium-gallium-zinc oxide (IGZO) with respect to negative bias illumination stress (NBIS). A plurality of IGZO devices is formed. Each of the plurality of IGZO devices includes a semiconductor substrate and an IGZO layer formed above the semiconductor substrate. A processing condition used to form at least two of the plurality of IGZO devices is varied in a combinatorial manner. A bias is applied to the semiconductor substrate of each of the plurality of IGZO devices. A current flow through each of the plurality of IGZO devices while the bias is applied is measured.

Abstract: An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds.

Abstract: Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.

Abstract: Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper.

Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.