Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.

Abstract: Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction. This combination of the two Schottky barriers provides current compliance during set operations and limits undesirable current overshoots during reset operations. The Schottky barriers' heights are configured to match the resistive switching characteristics of the cell. Conductive layers of the ReRAM cells operable as electrodes may be used to form these Schottky barriers together with semiconductor layers. These semiconductor layers may be different components from a variable resistance layer and, in some embodiments, may be separated by intermediate conductive layers from the variable resistance layers.

Abstract: Disclosed herein are systems, methods, and apparatus for forming adjustable windows may include a substrate and a first conducting oxide layer formed over the substrate. The adjustable windows may further include a spectral tuning layer formed over the first conducting oxide layer and an ion conductor layer formed over the spectral tuning layer. The adjustable windows may also include an ion storage layer formed over the ion conductor layer and a second conducting oxide layer formed over the ion storage layer. In some embodiments, the spectral tuning layer may be configured to change an infrared transmissivity of the adjustable window. Furthermore, the spectral tuning layer may be configured to toggle a solar heat gain ratio coefficient of the adjustable window between two or more solar heat gain ratio coefficients.

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including crystalline IGZO, a second sub-layer including amorphous IGZO, and a third sub-layer including magnesium and zinc. A source electrode and a drain electrode are formed above the IGZO channel layer.

Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.

Abstract: Ternary oxides, nitrides and oxynitrides of the form (a)(b)OxNy are formed by ALD or CVD when the reaction temperature ranges of the (a) precursor and the (b) precursor do not overlap. Chemically-reacted sub-layers, e.g., (a)OxNy, are formed by reacting the lower-temperature precursor with O and/or N at a temperature within its reaction range. Physisorbed sub-layers (e.g., (b) or (b)+ligand) are formed between the chemically-reacted sub-layers by allowing the higher-temperature precursor to physically adsorb to the low-temperature surface. When the desired sub-layers are formed, the substrate is heated to a temperature at which the higher-temperature precursor reacts (optionally in the presence of more O and/or N) to form (a)(b)OxNy. Quarternary and more complex compounds can be similarly formed.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is positioned relative to at least one target. The at least one target includes indium, gallium, zinc, or a combination thereof. A substantially constant voltage is provided across the substrate and the at least one target to cause a plasma species to impact the at least one target. The impacting of the plasma species on the at least one target causes material to be ejected from the at least one target to form an IGZO layer above the substrate.

Abstract: Systems and methods for rapid generation of ALD saturation curves using segmented spatial ALD are disclosed. Methods include introducing a substrate, having a plurality of substrate segment regions, into a processing chamber. The substrate may be disposed upon a pedestal within the chamber. Sequentially exposing the plurality of segment regions to a precursor within the chamber at a first processing temperature. Afterwards, purging the precursor from the chamber and then sequentially exposing each plurality of segment regions to a reactant within the chamber at the first processing temperature. Afterwards, purging the reactant from the chamber. Repeat sequentially exposing the plurality of segment regions to the precursor and the reactant for a plurality of cycles. Each segment region may be sequentially exposed to the precursor for a unique processing time. The pedestal may be rotated prior to exposing each next segment region to the precursor and the reactant.

Abstract: In some embodiments, apparatus are provided that provide for flexible processing in both high productivity combinatorial (HPC) and full wafer modes. The apparatus allow for interchangeable functionality that includes deposition with different sizes of targets, plasma treatment, ion beam treatment, and in-situ metrology. The functional modules are designed so that the modules may be interchanged with minimal effort and reduced system downtime.

Abstract: Solar cells and methods for forming a back contact layer for a solar cell are disclosed. The methods comprise depositing a first layer comprising a conductor on a substrate, depositing a second layer on the first layer, the second layer comprising between about 1 nm and about 25 nm of a metal chalcogenide, and forming a third layer operable as an absorber layer on the second layer. The absorber layer can comprise a photoactive semiconductor layer. In some embodiments, the absorber layer comprises a chalcogenide of copper-indium-gallium. In some embodiments, the absorber layer comprises a chalcogenide of copper-zinc-tin. In some embodiments, the absorber layer comprises CdTe. In some embodiments, the metal comprises Mo, W or Ta. In some embodiments, the metal comprises Mo. In some embodiments, the chalcogenide comprises S or Se or a combination thereof.

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An interface layer is formed above the gate dielectric material. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. The interface layer includes a material different than that of the gate dielectric layer and the IGZO channel layer.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a zirconium oxide-strontium-titanium oxide-zirconium oxide multilayer stack. The zirconium oxide can be replaced by at least one of hafnium oxide, aluminum oxide, magnesium oxide, or one of the lanthanide oxides.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A layer is formed above the substrate using a PVD process. The layer includes indium, gallium, zinc, or a combination thereof. The PVD process is performed in a gaseous environment having a pressure of between about 1 mT and about 5 mT and including between about 20% and about 100% oxygen gas. The PVD process may be performed at a processing temperature between about 25° C. and about 400° C. The duty cycle of the PVD process may be between about 70% and about 100%.

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract: In some embodiments, a “channel last” device architecture is implemented wherein an amorphous carbon layer is formed between the channel and the source and drain layers. Subsequent heating of the structure allows the metal materials in the source and drain layers to convert the amorphous carbon materials into graphene. This forms an ohmic contact between the source and drain layers and the channel layers and lowers the contact resistance.

Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.

Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Disclosed herein are systems, methods, and apparatus for forming windows that may include a substrate, a bottom dielectric layer formed over the substrate, and a reflective layer formed over the bottom dielectric layer. The windows may also include a conducting barrier layer formed over the reflective layer, an electrochromic layer formed over the conducting barrier layer, and an ion conductor layer formed over the electrochromic layer. The windows may further include an ion storage layer formed over the ion conductor layer and a conducting oxide layer formed over the ion storage layer. The electrochromic layer may be configured to change a transmissivity of the windows in response to a voltage being applied to the window. The windows may have an emissivity of between about 0.01 and 0.08.