Abstract: In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch.
Abstract: In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The plurality of source fingers is interdigitated with the plurality of drain fingers. Furthermore, an outer corner of the drain pad has a gradual transition between adjoining sides of the drain pad. The gradual transition between the adjoining sides of the drain pad reduces a termination electric field at the outer corner of the drain pad. Furthermore, the gradual transition between the adjoining sides of the drain pad increases the breakdown voltage of the semiconductor device.
Abstract: According to example configurations as described herein, a power supply system includes a unique circuit including an analog summer circuit, an analog-to-digital converter, and a digital controller. An output voltage feedback control loop of the power supply system feeds back the output voltage to the analog summer circuit. The analog summer circuit generates an analog error voltage signal based on: i) the output voltage received from the output voltage feedback loop, ii) an analog reference voltage signal, and iii) an analog reference voltage adjustment signal. The analog reference voltage adjustment signal varies depending on a magnitude of current provided by the output voltage to the dynamic load. Accordingly, the analog summer circuit can be configured to support adaptive voltage positioning. The analog-to-digital converter converts the analog error voltage signal into a digital error voltage signal. A controller generates output voltage control signal(s) based on the digital error voltage signal.
April 2, 2009
Date of Patent:
August 26, 2014
International Rectifier Corporation
Anthony B. Candage, Venkat Sreenivas, Gary D. Martin, Robert T. Carroll
Abstract: According to one disclosed embodiment, a power delivery circuit includes a switch for protection of a load in a reverse battery condition. The load is coupled in cascade with the protection switch, where the protection switch disconnects the load from the battery in the reverse battery condition. The protection switch does not include p-n junction diodes present in conventional protection switches using FETs. The protection switch utilizes, for example, a GaN HEMT, that does not include a p-n junction diode. Thus, the threat of internal conduction in the protection switch during a reverse battery condition is eliminated. The power delivery circuit also protects the load in a load dump condition.
Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.
November 30, 2011
Date of Patent:
August 19, 2014
International Rectifier Corporation
Timothy Phillips, Danny Clavette, EungSan Cho, Chuan Cheah
Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.
Abstract: There are disclosed herein various implementations of a short circuit protected composite switch and a circuit including such a switch. In one exemplary implementation, such a short circuit protected composite switch includes a III-N field-effect transistor (FET) having a drain, a source, and a gate, and a high current group IV FET coupled in series with the III-N FET and configured to limit a current through the III-N FET. The short circuit protected composite switch also includes another group IV FET coupled between the gate and the source of the III-N FET, and another transistor coupled between the gate of the III-N FET and a source of the high current group IV FET.
Abstract: In an exemplary implementation, a system for producing an electrical module includes a pressure chamber configured to receive a first body, a second body, and a sinter material therebetween. The system further includes a pressure generator configured to apply non-mechanical pressure in the pressure chamber to form the electrical module by attaching the first body to the second body using the sinter material. The pressure chamber is configured to enclose the first body over the second body. Furthermore, the pressure chamber includes a bottom opening configured to receive at least the first body. The non-mechanical pressure can include gas pressure.
Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.
Abstract: According to an exemplary embodiment, a power semiconductor package includes a power module having a plurality of power devices. Each of the plurality of power devices can be a power switch. The power semiconductor package also includes a double-sided heat sink with a top side in contact with a plurality of power device top surfaces and a bottom side in contact with a bottom surface of the power module. The power semiconductor package can include at least one fastening clamp pressing the top side and the bottom side of the double-sided heat sink into the power module. The double-sided heat sink can also include a water-cooling element.
Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
August 13, 2013
Date of Patent:
August 12, 2014
International Rectifier Corporation
Michael A. Briere, Paul Bridger, Jianjun Cao
Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
Abstract: An switch array for use in a motor control circuit with a power source, controller and a motor includes a plurality of bidirectional switches positioned between the power source and the motor, wherein the bidirectional switches are PWM controlled by high speed control signals from the controller to provide power from the power source to the motor as desired, wherein the switch array is positioned substantially adjacent to the motor. The power source may be a three phase AC power source. The switches are preferably bidirectional gallium nitride (GaN) switches.
Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.
Abstract: In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal.
Abstract: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.
Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.
Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.