Patents Assigned to International Rectifier Corporation
  • Patent number: 8791525
    Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: July 29, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
  • Publication number: 20140203295
    Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20140203294
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: International Rectifier Corporation
    Inventors: Robert Joseph Therrien, Jerry Wayne Johnson, Allen W. Hanson
  • Publication number: 20140203419
    Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
  • Patent number: 8786072
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 22, 2014
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 8786068
    Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: July 22, 2014
    Assignee: International Rectifier Corporation
    Inventors: Timothy A. Phillips, Danny Clavette, EungSan Cho, Chuan Cheah
  • Publication number: 20140197462
    Abstract: There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 k?-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source.
    Type: Application
    Filed: February 24, 2014
    Publication date: July 17, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20140197461
    Abstract: There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate.
    Type: Application
    Filed: December 24, 2013
    Publication date: July 17, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20140191337
    Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
  • Publication number: 20140192441
    Abstract: Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: International Rectifier Corporation
    Inventors: Michael A. Briere, Jason Zhang, Bo Yang
  • Patent number: 8766375
    Abstract: There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: July 1, 2014
    Assignee: International Rectifier Corporation
    Inventors: Tony Bramian, Jason Zhang
  • Publication number: 20140175630
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah
  • Publication number: 20140169052
    Abstract: According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: International Rectifier Corporation
    Inventor: Tony Bahramian
  • Publication number: 20140167112
    Abstract: In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can he situated over the group IV transistor die.
    Type: Application
    Filed: November 6, 2013
    Publication date: June 19, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20140167152
    Abstract: In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 19, 2014
    Applicant: International Rectifier Corporation
    Inventor: Ling Ma
  • Publication number: 20140167153
    Abstract: In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 19, 2014
    Applicant: International Rectifier Corporation
    Inventor: Ling Ma
  • Publication number: 20140159116
    Abstract: In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer.
    Type: Application
    Filed: November 20, 2013
    Publication date: June 12, 2014
    Applicant: International Rectifier Corporation
    Inventors: Michael A. Briere, Jin Wook Chung
  • Patent number: 8748204
    Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventor: Paul Bridger
  • Patent number: 8749034
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 8748298
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal