Abstract: A sliding-mode switching power supply (24) having N phases (28) and a method of operating the power supply (24) are provided. N switches (30) are coupled to a bipolar power source (22), with each switch (30) effecting one phase (28). An inductance (32) is coupled to each switch (30), and a capacitance (36) is coupled to the inductances (32). A load (26) is coupled across the capacitance (36). A monitor circuit (38) is coupled to the inductances (32) and the capacitance (36) and configured to monitor an output voltage (VOut) of the power supply (24). A first state-variable generator (42) generates a first state variable (first state variable x1) in response to the output voltage (VOut), and a second sate variable generator (44) synthesizes a second state variable (second state variable x2) from the first state variable (x1).

Abstract: A voltage regulator includes a voltage source for providing an input voltage and circuitry for regulating the input voltage to provide an output voltage. The circuitry for regulating the input voltage includes at least a high side switch and a low side switch. A skip mode controller controls the high side switch and the low side switch in order to minimize conduction losses and switching losses within the voltage regulator.

Abstract: A negative current generator for an amplifier circuit including a shunt transistor, first and second mirror transistors, a current bias device, and an amplifier. The amplifier circuit includes a current source transistor having current terminals coupled between a supply terminal and an input node and a control terminal receiving a bias voltage. The shunt transistor is coupled in a shunt configuration with the current source transistor. Each mirror transistor has a control terminal, a first current terminal coupled to the supply terminal and a second terminal coupled to a voltage node. The control terminal of the first mirror transistor receives another bias voltage. The current bias device draws a constant current from the voltage node. The amplifier has a first input receiving a reference voltage, a second input coupled to the voltage node, and an output coupled to the control terminals of the shunt and second mirror transistors.

Abstract: A multi-function circuit has as single input/control pin, to which respectively different values of a control input may be applied. A multi-function signal generation section is coupled to the single input/control pin and is operative to controllably generate a plurality of respectively different functional outputs, including a decoded address bit-representative output, a soft-start oscillator signal output, and a reset output, in response to application of respectively different values of the control input.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Abstract: A MOSFET-based, multi signal-switching circuit controllably passes analog/audio signals and digital signals through a common terminal to a single connector. Analog/audio signals are coupled through a single N-channel MOSFET analog signal switch which, when turned-ON, minimizes distortion of the analog/audio signal and capacitive loading to an adjacent, MOS-based or CMOS-based digital data signal switch. A respective turn-OFF circuit maintains its associated switch MOSFET turned OFF.

Abstract: A sliding-mode switching power supply (24) having N phases (28) and a method of operating the power supply (24) are provided. N switches (30) are coupled to a bipolar power source (22), with each switch (30) effecting one phase (28). An inductance (32) is coupled to each switch (30), and a capacitance (36) is coupled to the inductances (32). A load (26) is coupled across the capacitance (36). A monitor circuit (38) is coupled to the inductances (32) and the capacitance (36) and configured to monitor currents (IL) through the inductances (32) and/or a voltage (VC) across the capacitance (36). A sliding-surface generator (78) is coupled to the monitor circuit (38) and generates a single sliding surface (?) for all phases (28). A constant-frequency control (104) forms a variable window (??) for the sliding surface (?). A switching circuit (138) switches the switches (30) at a switching frequency (fS) determined by the variable window (??).

Abstract: Apparatus for providing over-current protection in a power converter device includes a first circuit for providing high-side sinking over-current protection for the power converter device responsive to a phase signal and a high-side over-current signal of the power converter device. A second circuit provides low-side sinking over-current protection for the power converter device responsive to the phase signal and the low-side over-current signal of the power converter device. Finally, a third circuit provides low-side sourcing over-current protection responsive to the phase signal, the low-side over-current protection signal and a power ground signal of the power converter device.

Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

Abstract: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm?1.

Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

Abstract: A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells). Buildcode representations are then assigned for each of a plurality of circuit components and features thereof to realize customization of at least a portion of the plurality of p-cells. A final layout of the custom integrated circuit is then generated using the buildcode representations.

Abstract: A circuit and corresponding method for a precision floating gate voltage reference that uses a feedback loop, conduction of tunnel devices, and a bandgap cell to accurately program a desired charge level on a floating gate and provide a predictable and programmable temperature coefficient parameter for such voltage reference. In one embodiment, a bandgap cell is coupled through a capacitor to the floating gate storage node for providing a voltage source for canceling the temperature coefficient (TC) of the storage capacitor. The circuit and method enables TC to be minimized by either choosing the proper voltage source characteristics or alternatively, by choosing the proper ratio of two capacitors. The bandgap cell can alternatively be designed to have positive TC (PTAT voltage sources) or negative TC (VBE junction).

Abstract: Systems and methods for slow tail compensation are provided. A photodetector signal is pre-amplified to thereby produce an uncompensated photodetector signal that includes a fast component and a slow component. The fast component is removed from the uncompensated photodetector signal to thereby produce a compensating signal that includes the slow component of the uncompensated photodetector signal. The compensating signal is subtracted from the uncompensated photodetector signal to thereby produce a compensated photodetector signal that includes the fast component but not the slow component.

Abstract: A PWM control circuit for a voltage regulator including a compensation network, a ramp generator providing a ramp voltage, an offset adjust circuit and a comparator circuit. The compensation network senses the output voltage, receives a reference voltage, and outputs a compensation voltage. The offset adjust circuit adjusts a selected one of the ramp voltage and the compensation voltage based on the reference voltage. The comparator circuit compares the compensation voltage with the ramp voltage and provides a PWM signal for controlling the output voltage. The offset adjust circuit may generate an offset voltage based on the reference voltage and a gain G of the voltage regulator. The offset adjust circuit may subtract the offset voltage from either the ramp voltage or the compensation voltage to provide an adjusted voltage to the comparator circuit.

Abstract: An adaptive pulse positioning system for a voltage converter providing an output voltage, the system including a PWM generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal. A method of adaptively positioning PWM pulses that are used to control an output voltage of a voltage regulator including generating a series of PWM pulses based on a clock signal, sensing an output load condition, and adaptively shifting the series of PWM pulses based on the output load condition.

Abstract: A semi-clockless, cascaded, current-mode regulator has a first regulator that receives a clock signal from a controller. By ‘semi-clockless’ is meant that a clock signal is applied to the first of a cascaded plurality of regulators, and that as a result of the cascading of clock delay circuits in each of the regulators, the remaining regulators receive sequentially delayed versions of the clock signal applied to the first regulator. The regulators are coupled to control the operations of associated pulse width modulation controlled switching circuits. Outputs of the switching circuits are combined to realize a multi-phase output voltage.

Abstract: An apparatus and method for disabling a charging counter circuitry within a battery charger is disclosed. The apparatus includes circuitry connected to a pin associated with the charging counter circuitry of the battery charger, said circuitry receiving a signal from a device connected to the battery charger. The circuitry disables the charging counter circuitry responsive to a signal from the device at a first level and enables the charging counter circuitry responsive to the signal from the device at a second level.

Abstract: A method of enabling and disabling diode emulation for a DC/DC converter which generates an output voltage including detecting a diode emulation request signal indicative of enabling or disabling diode emulation and delaying enabling or disabling diode emulation until after the output voltage begins changing. Diode emulation is enabled while the output voltage is decreasing or has reached a predetermined level and an optional delay may be included. Diode emulation is disabled while the voltage is increasing. A diode emulation control circuit includes a first circuit that determines when the output voltage is changing and a second circuit that selectively enables or disables diode emulation in response to a diode emulation enable/disable signal after the output voltage begins to change.